SSTUA32866 Philips Semiconductors, SSTUA32866 Datasheet - Page 20

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SSTUA32866

Manufacturer Part Number
SSTUA32866
Description
configurable registered buffer
Manufacturer
Philips Semiconductors
Datasheet

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Product data sheet
11.4 Partial parity out load circuit and voltage measurement information
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
Fig 24. Partial parity out load circuit
Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock
DD
= 1.8 V
(1) C
10 MHz; Z
clock inputs
V
t
V
inputs
PLH
TT
i(p-p)
L
includes probe and jig capacitance.
= V
and t
= 600 mV
0.1 V.
DD
PHL
/2
0
waveform 2
= 50 ; input slew rate = 1 V/ns
are the same as t
CK
CK
output
timing
inputs
Rev. 01 — 15 July 2005
output
1.8 V DDR2-667 configurable registered buffer with parity
DUT
t
V
PLH
OUT
PD
ICR
.
V
t
LH
ICR
C
0.15 V
L
= 5 pF
(1)
V
ICR
20 %, unless otherwise specified.
t
V
V
PHL
TT
ICR
test point
R
002aaa375
002aaa654
L
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
002aaa503
= 1 k
SSTUA32866
V
i(p-p)
V
V
V
0 V
OH
OL
V
OH
i(p-p)
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