MT9043 Zarlink Semiconductor, MT9043 Datasheet - Page 8

• Manufacturer Part Number: MT9043
• Description: T1/E1 System Synchronizer
• Manufacturer: Zarlink Semiconductor

All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL for a complete loss of incoming signal, or a large frequency shift in
the incoming signal. If the input signal is outside the Impairment Monitor Capture Range the PLL automatically
changes from Normal Mode to Free Run Mode. See AC Electrical Characteristics - Performance for the Impairment
Monitor Capture Range. When the incoming signal returns to normal, the DPLL is returned to Normal Mode.
State Machine Control
As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit and the
DPLL. Control is based on the logic levels at the control inputs RSEL and MS (See Figure 6).
All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation
section for full details.
Master Clock
The MT9043 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Control and Mode of Operation
The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2.
The MT9043 has two possible modes of operation, Normal and Freerun.
Figure 6 - Control State Machine Block Diagram
RSEL
RSEL
MS
0
1
0
1
Table 3 - Operating Modes and States
Select MUX
Table 2 - nput Reference Selection
Reference
To
Zarlink Semiconductor Inc.
State Machine
MT9043
Corrector
To TIE
Enable
Control
MS
Input Reference
8
FREERUN
NORMAL
Mode
SEC
PRI
To DPLL
Select
State
Data Sheet