MT9043 Zarlink Semiconductor, MT9043 Datasheet - Page 11

• Manufacturer Part Number: MT9043
• Description: T1/E1 System Synchronizer
• Manufacturer: Zarlink Semiconductor

Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is
nominally equal to the value of the final output signal or final input signal.
Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has
settled to a steady state.
In the case of the MT9043, the output signal phase continuity is maintained to within
frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type of
mode change, may accumulate up to 200 ns over many frames. The rate of change of the 200 ns phase shift is
limited to a maximum phase slope of approximately 5ns/125us. This meets the AT&T TR62411 maximum phase
slope requirement of 7.6ns/125us and Bellcore GR-1244-CORE (81ns/1.326ms).
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
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Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9043 loop filter and
limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,
phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical
Characteristics - Performance for Maximum Phase Lock Time.
MT9043 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference
within approximately 500 ms.
initial input to output phase difference
initial input to output frequency difference
synchronizer loop filter
synchronizer limiter
MTIE S ( )
=
TIEmax t ( ) TIEmin t ( )
Zarlink Semiconductor Inc.
MT9043
11
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±
5ns at the instance (over one
Data Sheet