MT9043 Zarlink Semiconductor, MT9043 Datasheet - Page 3

• Manufacturer Part Number: MT9043
• Description: T1/E1 System Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description
33,34
Pin #
11
12
13
14
15
16
18
19
20
21
22
24
25
26
27
29
30
32
36
37
9
FLOCK
Name
C1.5o
LOCK
OSCi
C19o
C16o
F16o
RSP
TSP
C6o
C2o
C4o
C8o
F0o
F8o
MS
NC
IC
IM
IC
IC
IC
Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is
connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is
connected to a clock source, see Figure 8.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mb/s. See Figure 14.
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 2.048Mb/s and 4.096Mb/s. See Figure 14.
Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks
the beginning of a frame. See Figure 14.
Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to
the input reference.
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.
Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less
than 500 ms locking time).
Internal Connection. Tie low for normal operation.
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384MHz clock.
Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
Impairment Monitor (CMOS Output). A logic high on this pin indicates that the Input
Impairment Monitor has automatically put the device into Freerun Mode.
Internal Connection. Tie high for normal operation.
No Connection. Leave open circuit.
Internal Connection. Tie low for normal operation.
Mode/Control Select (Input). This input determines the state (Normal or Freerun) of
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3.
Internal Connection. Tie low for normal operation.
Zarlink Semiconductor Inc.
MT9043
3
Description
Data Sheet