MT9043 Zarlink Semiconductor, MT9043 Datasheet - Page 5

• Manufacturer Part Number: MT9043
• Description: T1/E1 System Synchronizer
• Manufacturer: Zarlink Semiconductor

Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or
SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.
During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary
reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL
would lead to unacceptable phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the
signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is
input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.
During a switch from one reference to the other, the State Machine first changes the mode of the device
from Normal to Freerun. The Compare Circuit then measures the phase delay between the current phase
(feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable
Delay Circuit (See Figure 3). The state machine then returns the device to Normal Mode and the DPLL begins
using the new virtual reference signal. The difference between the phase position of the new virtual reference and
the previous reference is less than 1 µs.
Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual
reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.
This phase error is a function of the difference in phase between the two input reference signals during reference
PRI or SEC
Select Mux
Reference
from
Programmable
0
1
Delay Circuit
FS2
0
1
Table 1 - Input Frequency Selection
Figure 3 - TIE Corrector Circuit
Zarlink Semiconductor Inc.
FS1
0
1
0
1
MT9043
State Machine
TIE Corrector
Control
Circuit
Enable
TCLR
from
5
Resets Delay
Input Frequency
Delay Value
19.44MHz
1.544MHz
2.048MHz
Control Signal
8kHz
Select MUX
Signal from
Frequency
Feedback
Compare
Circuit
Reference
to DPLL
Virtual
Data Sheet