MT28C3224P20 Micron Technology, MT28C3224P20 Datasheet - Page 23

• Manufacturer Part Number: MT28C3224P20
• Description: FLASH AND SRAM COMBO MEMORY
• Manufacturer: Micron Technology

protection configuration register, the READ ARRAY
command, FFh, must be issued to the bank containing
address 00h prior to issuing other commands.
LOCKING OPERATIONS DURING ERASE
SUSPEND
ing an ERASE SUSPEND by using the standard locking
command sequences to unlock, lock, or lock down. This
is useful in the case when another block needs to be
updated while an ERASE operation is in progress.
tion, first write the ERASE SUSPEND command (B0h),
then check the status register until it indicates that the
ERASE operation has been suspended. Next, write the
desired lock command sequence to block lock, and the
lock status will be changed. After completing any de-
sired LOCK, READ, or PROGRAM operations, resume
the ERASE operation with the ERASE RESUME com-
mand (D0h).
SUSPEND on the same block, the locking status bits
are changed immediately. When the ERASE is resumed,
the ERASE operation completes.
PROGRAM SUSPEND.
STATUS REGISTER ERROR CHECKING
quences during ERASE SUSPEND can introduce ambi-
guity into status register results.
invalid command produces a lock command error (SR4
and SR5 are set to “1”) in the status register. If a lock
command error occurs during an ERASE SUSPEND,
SR4 and SR5 are set to “1” and remain at “1” after the
ERASE SUSPEND command is issued. When the ERASE
is complete, any possible error during the ERASE can-
not be detected via the status register because of the
previous locking command error.
a program operation error nested within an ERASE
SUSPEND.
CHIP PROTECTION REGISTER
fullfill the security considerations in the system (pre-
venting device substitution).
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Changes to block lock status can be performed dur-
To change block locking during an ERASE opera-
If a block is locked or locked down during an ERASE
A locking operation cannot be performed during a
Using nested locking or program command se-
Following protection configuration setup (60h), an
A similar situation happens if an error occurs during
A 128-bit chip protection register can be used to
23
256K x 16 SRAM COMBO MEMORY
segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit number. The
other segment is left blank for customers to program as
desired. (See Figure 9).
READING THE CHIP PROTECTION REGISTER
identification mode, loading the 90h command. Once
in this mode, READ cycles from addresses shown in
Table 9 retrieve the specified information. To return to
the read array mode, write the READ ARRAY command
(FFh).
PAGE READ MODE
same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0–A1 allows random ac-
cess of other words in the page.
four or eight words as required; but if no specification is
made, the normal size is four words.
ASYNCHRONOUS READ CYCLE
when switching between pages, the access time is given
by
on the data bus and the processor can read the data.
t
The 128-bit security area is divided into two 64-bit
The chip protection register is read in the device
The initial portion of the page mode cycle is the
The page size can be customized at the factory to
When accessing addresses in a random order or
When F_CE# and F_OE# are LOW, the data is placed
AA.
Protection Register Memory Map
88h
85h
84h
81h
80h
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2 MEG x 16 PAGE FLASH
Factory-Programmed
PR Lock
User-Programmed
Figure 9
4 Words
4 Words
0
©2002, Micron Technology, Inc.
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