MT28C3224P20 Micron Technology, MT28C3224P20 Datasheet

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... Dual 64-bit chip protection registers for security purposes 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S ...

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... MT28C3224P20FL-80 BET MT28C3224P20FL-80 TET MT28C3224P18FL-85 BET MT28C3224P18FL-85 TET 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY The separate S_V retention capability when required. The data reten- tion S_V MT28C3224P20 and MT28C3224P18 devices support two V 2.2V and a production compatibility voltage of 12V ± ...

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... MT28C3224P20FL-80 BET MT28C3224P20FL-80 TET MT28C3224P18FL-85 BET MT28C3224P18FL-85 TET 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY Valid combinations of features and their correspond- ing part numbers are listed in Table 2. Figure 1 Part Number Chart ...

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... F_CE# CSM F_WE# F_OE# WSM I/O Logic Address Input A0–A20 Buffer Address Latch 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY BLOCK DIAGRAM F_V F_V CC PP Bank a FLASH 2,048K x 16 Bank b SRAM ...

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... C8, B10, F8, F7, E8, E6, D7, C7, B9 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0– ...

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... A12, C4, H1, H2, H10, H11, H12 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY Flash Program/Erase Power Supply: [0.9V–2.2V or 11.4V–12.6V]. Operates as input at logic levels to control complete device protection. Provides backward compatibility for factory programming when driven to 11.4V– ...

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... Data output on upper byte only; lower byte High-Z. 9. Data input on lower byte only. 10. Data input on upper byte only. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY SRAM SIGNALS H SRAM must be High-Z ...

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... Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY Figure 2 Bottom Boot Block Device Address Range Block (x16) (K-bytes/K-words) 1F8000h-1FFFFFh 22 1F0000h-1F7FFFh 21 1E8000h-1EFFFFh 20 1E0000h-1E7FFFh 19 1D8000h-1DFFFFh 18 1D0000h-1D7FFFh 17 1C8000h-1CFFFFh ...

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... Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY Figure 3 Top Boot Block Device Address Range Block (x16) (K-bytes/K-words) 1FF000h-1FFFFFh 47 1FE000h-1FEFFFh 46 1FD000h-1FDFFFh 45 1FC000h-1FCFFFh 44 1FB000h-1FBFFFh 43 1FA000h-1FAFFFh 42 1F9000h-1F9FFFh ...

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... B0h C0h D0h FFh 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY logic LOW level (V logic HIGH (V Table 6 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. ...

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... SRD: Data read from the status register WA: Word address of memory location to be written, or read WD: Data to be written at the location WA 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 3 ...

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... First Protection Register Lock Device First Protection Register 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY Table 5 Command Descriptions DESCRIPTION Operates the same as a PROGRAM SETUP command. ...

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... D0h Unlock Block Second 00h Invalid/Reserved 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY Table 5 DESCRIPTION If the previous command was an ERASE SETUP command, then the CSM closes the address and data latches, and it begins erasing the block indicated on the address pins ...

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... DQ0–DQ7 to the bank containing address 00h 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY and the identification code address on the address lines ...

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... Standby Output Disable Reset Write 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY plished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid ad- dress within that block ...

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... BLOCK LOCK STATUS (BLS PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted Operation to Locked Blocks SR0 RESERVED FOR FUTURE ENHANCEMENT 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY Table 7 Status Register Bit Definition ...

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... SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY BUS ...

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... Issue READ ARRAY Command NO Finished Reading ? YES Issue PROGRAM RESUME Command PROGRAM Resumed 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND COMMENTS WRITE READ Standby Standby WRITE READ WRITE ...

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... SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY BUS ...

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... ERASE Continued NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure. 2. See Word Programming Flowchart for complete programming procedure. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND COMMENTS ...

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... MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY BLOCK LOCKING The Flash memory of the MT28C3224P20 and MT28C3224P18 devices provide a flexible locking scheme which allows each block to be individually locked or unlocked with no latency. The devices offer two-level protection for the blocks. ...

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... NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. “XX” specifies the block address of lock configuration. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY Table 8 Block Locking State Transition ...

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... A 128-bit chip protection register can be used to fullfill the security considerations in the system (pre- venting device substitution). 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY The 128-bit security area is divided into two 64-bit segments ...

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... WRITE/ERASE operations when Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY During WRITE and ERASE operations, the WSM monitors the V tions are allowed only when V specified in Table 10. (MAX). If the ...

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... Q/2. Input rise and fall times (10% to 90%) < 5ns Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to PP the device ...

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... This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY 1 ...

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... This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY 1 ...

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... OE# LOW to output delay F_RP# HIGH to output delay CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change READ cycle time 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY SYMBOL C C ...

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... Word program time 4KW parameter block erase time 32KW parameter block erase time Program suspend latency Erase suspend latency 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY SYMBOL MIN t ...

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... DH 0 NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY VALID ADDRESS VALID ADDRESS t AS ...

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... SYMBOL MIN MAX ACE 80 t AOE 25 t RWH 200 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY VALID ADDRESS ACE t RWH -85 = 1.70V–1.90V MIN MAX UNITS ...

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... SYMBOL MIN MAX ACE 80 t APA 30 t AOE 25 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY VALID ADDRESS VALID VALID ADDRESS ADDRESS ACE t AOE VALID High-Z OUTPUT t ...

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... V = 1.80V–2.20V SYMBOL MIN MAX t RWH 200 t RP 100 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY RESET OPERATION t RP -85 = 1.70V–1.90V MIN MAX UNITS 250 ns 100 ns 33 ...

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... Top boot block device ……48 blocks of 002F, 0000 Bottom boot block device ……48 blocks of 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY Table 11 CFI DESCRIPTION n ...

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... SRAM density, 4Mb (256K x 16) 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY Table 11 CFI (continued) DESCRIPTION n user programmable bytes Micron Technology, Inc ...

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... A4–A17 S_CE1# S_CE2 S_WE# S_OE# S_UB# S_LB# 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY S_OE addresses A0–A3. S_UB# and S_LB# control the data width as described above When in this SRAM WRITE ARRAY ...

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... Write pulse width Write recovery time Write to High-Z output Data to write time overlap Data hold from write time End write to Low-Z output 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY to 0. ...

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... CO 100 LB, UB 100 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY READ CYCLE 1 ; S_CE2, S_WE PREVIOUS DATA VALID READ CYCLE 2 (S_WE ...

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... LBW, UBW Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY WRITE CYCLE (S_WE# CONTROL LBW, t UBW High-Z t WHZ -80/-85 MAX UNITS ...

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... LBW, UBW Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY WRITE CYCLE 2 (S_CE1# CONTROL LBW, t UBW WHZ -80/-85 MAX UNITS ...

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... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 256K x 16 SRAM COMBO MEMORY 66-BALL FBGA 8 ...

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... Updated notes for Combined DC Characteristics Original document, Rev. 1, ADVANCE ....................................................................................................................... 12/01 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. ...