XC2C512 Xilinx, XC2C512 Datasheet - Page 2

• Manufacturer Part Number: XC2C512
• Description: Coolrunner-ii CPLD
• Manufacturer: Xilinx

XC2C512 CoolRunner-II CPLD
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is output
banking. Four output banks are available on the
CoolRunner-II 512 macrocell device that permits easy inter-
facing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
The CoolRunner-II 512 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital, a design technique that makes use of CMOS
technology in both the fabrication and design methodology.
RealDigital design technology employs a cascade of CMOS
gates to implement sum of products instead of traditional
sense amplifier methodology. Due to this technology, Xilinx
CoolRunner-II CPLDs achieve both high-performance and
low power operation.
Table 2: I
2
Notes:
1.
Typical -7, -10 I
Typical -6 I
16-bit up/down, resettable binary counter (one counter per function block).
CC
CC
vs Frequency (LVCMOS 1.8V T
(mA)
CC
(mA)
150
250
200
100
50
0
0
0.025
0
20
40
17.22
Table
20
A
Figure 1: I
= 25°C)
60
1). This
www.xilinx.com
1-800-255-7778
34.37
Frequency (MHz)
80
40
(1)
CC
vs Frequency
100
Supported I/O Standards
The CoolRunner-II 512 macrocell features LVCMOS,
LVTTL, SSTL, and HSTL I/O implementations. See
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL I/O standards make use of a V
for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V
I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C512
For information on Vref pins, see XAPP399.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
1.5V I/O
HSTL-1
SSTL2-1
SSTL3-1
52.04
I/O Types
60
120
Frequency (MHz)
140
69.44
80
-7 -10
Output
160
V
CCIO
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
86.85
DS096_01_022003
100
180
Preliminary Product Specification
V
Input
200
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
108.61
DS096 (v2.5) January 30, 2005
125
Input
V
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
REF
130.37
150
Termination
Voltage V
Board
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
Table 1
REF
200
TT
pin
R