TSS463 ATMEL Corporation, TSS463 Datasheet - Page 7

no-image

TSS463

Manufacturer Part Number
TSS463
Description
VAN Data Link Controller with Serial Interface
Manufacturer
ATMEL Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TSS463
Manufacturer:
ATMEL
Quantity:
20 000
Part Number:
TSS463AA
Manufacturer:
E-SWITCH
Quantity:
4 600
Part Number:
TSS463AAR
Manufacturer:
SILI
Quantity:
3 350
Part Number:
TSS463ATERZ
Manufacturer:
ATMEL
Quantity:
4 233
Part Number:
TSS463B-9
Manufacturer:
ATMEL
Quantity:
210
Part Number:
TSS463B-9
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
TSS463B-E9
Manufacturer:
ATMEL
Quantity:
430
Part Number:
TSS463C
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
TSS463C-E9
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
SPI Control Byte
DIR: Serial Transfer Direction
4102E–AUTO–12/04
Figure 4. CPOL and CPHA in the TSS463B
At the beginning of a transmission over the serial interface, the first byte is the address
of the TSS463B register to be accessed. The next byte transmitted is the control byte
that determines the direction of the communication. The following bytes are data bytes
(consecutive bytes are written in or read from Address, Address + 1, Address + 2, ...,
Address + n with n = 0 to 28).
To make sure the TSS463B is not out of synchronization, the SPI interface will transmit
data ’0xAA’and ’0x55’on the MISO pin during address and control byte time. This way,
the master always ensures the TSS463B is well-synchronized. If the TSS463B is out of
synchronization, the master can assert the SS pin inactive to resynchronize the SPI
interface or can assert the RESET pin active or can send an initialization sequence.
When the SS pin is inactive, the SCLK is allowed to toggle. This will have no effect on
the TSS463B SPI module.
The SPI control byte is transmitted by the master (CPU) to the TSS463B. It specifies
whether it is a TSS463B Write or Read.
Table 1. SPI Control Byte
Zero: Read Operation. The data bytes will be read by the master (CPU) from the
TSS463B.
One: Write Operation. The data bytes will be written by the master (CPU) to the
TSS463B.
In both cases, address auto-increment mechanism will take place when more than one
data byte is read or written. This mechanism is inhibited when address value reaches
0xFF.
The seven following bits are reserved and must be equal to: 1100000.
When the master (CPU) conducts a write, it sends an address byte, a control byte and
data bytes on its MOSI line. The slave device (TSS463B) will send, if well-synchronized,
’0xAA’during the address byte and ’0x55’during the control byte on its MISO line.
DIR
7
6
1
SPI 8 Pulses
5
1
SCLK
MOSI
MISO
SS
4
0
Data T ransmit Points
CPOL = CPHA = 1
Data Sample Points
0x55
0x66
3
0
2
0
TSS463B
1
0
0
0
7

Related parts for TSS463