TSS463 ATMEL Corporation, TSS463 Datasheet - Page 5

• Manufacturer Part Number: TSS463
• Description: VAN Data Link Controller with Serial Interface
• Manufacturer: ATMEL Corporation

Microprocessor
Interface
Interface Modes
Motorola SPI Mode
4102E–AUTO–12/04
The processor controls the TSS463B by reading and writing the internal registers of the
circuit. These registers appear to the processor as regular memory locations.
The TSS463B must be connected with an SPI or SCI serial interface.The following sec-
tion provides information switching from one mode to another.
The first two bytes to be sent by the master (CPU) are called ’Initialization Sequence’:
This sequence provides a proper asynchronous RESET in the TSS463B and it selects
the Motorola SPI, Intel SPI or the SCI serial mode. This initialization sequence is shown
on figure 4: two 0x00 will cause an internal RESET and assert the Motorola SPI mode,
two ’0xFF’ will provide an internal RESET and assert the Intel SPI mode and ’9 bits to 0
followed by 0xFF or 0xFE’will generate an internal RESET and assert the 9-bits SCI
mode.
Figure 2. Mode Configuration Byte
The Motorola Serial Peripheral Interface (SPI) is fully compatible with the SPI Motorola
protocol. The interface is implemented for slave-mode only (the TSS463B can not gen-
erate SPI frames by itself).
The SPI interface allows the interconnection of several CPUs and peripherals on the
same printed circuit board.
The SPI mode interface consists of 4 pins: separate wires are required for data and
clock, so the clock is not included in the data stream as shown on Figure 3. One pin is
needed for the serial clock (SCLK), two pins for data communication MOSI and MISO
and one pin for Slave Select (SS)
Internal RESET
Internal RESET
SCLK
MOSI
SCLK
MOSI
SS
SS
Internal RESET and SPI Mode (Intel or Motorola)
0 . 0000 . 0000
or
Internal RESET and SCI Mode
0x00
0xFF
SPI 8 Pulses
SCI 9 Pulses
0x00
0xFF
1 . 1 111 . 1111
Motorola
Intel
TSS463B
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