TSS463 ATMEL Corporation, TSS463 Datasheet - Page 29

• Manufacturer Part Number: TSS463
• Description: VAN Data Link Controller with Serial Interface
• Manufacturer: ATMEL Corporation

SDC [3:0]: SDC Divider
Ma, Mb: Operating Mode
Command Bits
4102E–AUTO–12/04
•
The input clock is the timeslot clock.
Table 6. System Diagnosis Clock Divider
Table 7. Diagnosis System Command Bits
SDC calculation: (see “SDC Signal (Synchronous Diagnosis Clock)” on page 24).
Notes:
Example: For VAN frame speed rate = 62,5 KTS/s (1 TS = 16 µs), SDC >100 ms
In the two low order bits, the user controls if the SDC and TIP are to be generated
automatically ETIP, ESDC.
Ma
1. For each module, determine the largest interframe spacing, LIFS (*).
2. For the whole network, get the maximum LIFS, MAX-LIFS.
3. SDC period > MAX-LIFS.
0
0
1
1
(*) IFS min. = 4 TS
SDC DIVIDER SDC [3:0]
=> 100 ms / 16 µs = 6250, divider chosen: 8192, SDC [3:0] = 0111.
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
Mb
0
1
0
1
Forces the Communication on RxD0 (differential)
Forces the Communication on RxD2 (DATA)
Forces the Communication on RxD1 (DATA)
Automatic selection
Divide by
1048576
2097152
131072
262144
524288
16384
32768
65536
1024
2048
4096
8192
128
256
512
64
TSS463B
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