MT8926AE Zarlink Semiconductor, MT8926AE Datasheet - Page 6

• Manufacturer Part Number: MT8926AE
• Description: MT8926 - T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

times a second) the state of these registers and counters is recorded in a set of snap-shot registers. This data in the
snap-shot registers is then inserted into the appropriate bit positions of the ST-BUS status stream CSTo.
FDL bit-oriented messages can be communicated via the PMAC transmit and receive bit-oriented message
registers. The user gains access to these registers through the ST-BUS control streams. Valid
messages consist of a series of repeating 16 bit code words of the form: 11111111 0XXXXXX0, where XXXXXX is
the message content. The PMAC will automatically append the prefix byte 11111111 to the transmit message and
remove it from the receive message. It will also indicate the reception of a valid message. When bit-oriented
messages are not being transported, message-oriented facility data link signals, assembled by an external HDLC
controller (i.e., MT8952), can be passed through the PMAC to the MT8976/77 for transmission.
The PMAC can implement an ESF payload loopback by routing the MT8976/77 DSTo stream to the MT8976/77
DSTi input (see Figure 6 on page 8). The payload loopback is controlled through the loopback control word,
Channel 15 of CSTi1 (see Figure 3 on page 5). When the payload loopback is disabled, data entering the PMAC’s
DSTi0 pin is transferred to the PMAC DSTo. DSTo of the PMAC should be connected to the DSTi pin of the
MT8976/77 framer.
1.1
The MT8926 PMAC is designed to function with the MT8976/77 T1 framer. Figure 9 on page 21 illustrates a typical
application and the connections involved in realizing this interface. Both the PMAC and framer receive the extracted
clock and data from the T1 line interface. This allows the MT8926 to perform B8ZS recovery and BPV detection, as
well as SF or ESF synchronization, framing error detection, facility data link extraction, and line loopback code
detection.
Some of the CSTi1 channels that are not used to control the MT8976/77 are used to control the PMAC, therefore,
CSTi1 will connect to both devices. Figure 3 on page 5 shows the channels of CSTi1 that carry the MT8976/77 Per
Channel Control Words, as well as the MT8926 control data. C2i and F0i supply timing references for both devices.
The CSTo stream of the MT8976/77 framer enters the PMAC on CSTi0 (see Figure 4 on page 6). The PMAC adds
its performance data to form the CSTo stream of the PMAC. Figure 5 on page 8 shows the channels and status bits
that the PMAC has added to CSTo. E8Ko of the framer will also pass through the PMAC, E8Ki to E8Ko, under
control of CSTi1.
MT8926
6
T1
MT8976/77
PCSW
PSW
MSW
CSTi0
CSTo
=
=
=
Figure 4 - MT8926 CSTi0 (MT8976/77 CSTo) Channel Allocation Versus T1 Channels
PMAC - Framer Interworking
PCSW
0-2
1-3
Per Channel Status Word
Phase Status Word
Master Status Word
PS
W
3
PCSW
4-6
4-6
7
X
PCSW
8-10
7-9
11
X
PCSW
12-14
10-12
MS
W1
15
PCWS
16-18
13-15
19
X
PCSW
20-22
16-18
23
X
PCSW
24-26
19-21
27
X
Data Sheet
PCSW
24-26
22-24
bit-oriented
SEMICMF.019
MS
W2
31