MT8926AE Zarlink Semiconductor, MT8926AE Datasheet
MT8926AE
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MT8926AE Summary of contents
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... DSTi1 Loopback Control DSTo F0i SEMICMF.019 ISO-CMOS ST-BUS DS5718 MT8926AE MT8926AP Description The MT8926 Performance Monitoring Adjunct Circuit (PMAC) interworks with Mitel's MT8976/77 and MH89760B to provide performance monitoring data, alarms and T1 maintenance features. It meets the performance monitoring and maintenance requirements of ANSI T1.403 and T1.408, and also supports Channel Service Unit (CSU) requirements ...
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MT8926 1 VSS ECLK 2 RxA 3 4 RxB E8Ki E8Ko 7 8 VSS 9 CSTo 10 CSTi0 11 CSTi1 F0i 12 C2i 13 VSS 14 28 PIN PLASTIC DIP 2 28 VDD DSTi1 ...
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Data Sheet Pin Description Table Pin # Name 1 V System Ground ECLK Extracted Clock Input. A 1.544 MHz clock derived from the received data. This signal is used to clock in the data on pins RxA and ...
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MT8926 Pin Description Table (continued) Pin # Name 18 FDLo Facility Data Link Output. When bit-oriented messaging is enabled (i.e., PMAC Control Word bit 0, FDLEn, is high), data in the Transmit BOM register will be appended to a 1111 ...
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Data Sheet 1.0 Functional Description The MT8926 Performance Monitoring Adjunct Circuit (PMAC) is designed to enable a MT8976/77 based T1 interface to gather performance data and perform maintenance functions as per ANSI T1.403 and T1.408. Performance data collection includes CRC ...
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MT8926 times a second) the state of these registers and counters is recorded in a set of snap-shot registers. This data in the snap-shot registers is then inserted into the appropriate bit positions of the ST-BUS status stream CSTo. FDL ...
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Data Sheet It should be noted that the PMAC will replace some of the data of MT8976/77 Master Status Words 1 and 2. This is outlined in Table 1 on page 7 and Table 2 on page 7. Table 1 ...
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MT8926 0-2 3 4-6 7 CSTo PS PCSW PM PCSW PCSW 1-3 4-6 Cyclic Redundancy Check-6 Error Counter PMAC Miscellaneous Status Word Bit Bit Function 7 0 7-5 Not Used 4 LLDD (001) 3 LLED (00001) 2 ...
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Data Sheet Bit Name 7-6 YLALR These bits (Yellow Alarm Indication and Mimic) contain information from the & MT8976/77 that is unaltered by the MT8926. See Master Status Word 1 of the MIMIC MT8976/77 data sheet. 5 ALRM Alarm. This ...
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MT8926 1.4 Remote Alarm Indication (RAI) The PMAC will decode the bit-oriented priority codeword 11111111 00000000 received on the FDL as a Remote Alarm Indication (RAI or Yellow Alarm) signal as per T1.403/408. See the section on MT8926 FDL message ...
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Data Sheet Bit Name 2 FECV Framing Error Count Validation. This bit is set when the MT8926 has synchronized to a framed T1 signal. The framing error count is frozen if this bit is not set. Synchronization (FECV=1) is reported ...
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MT8926 1.9 Timer Outputs The PMAC has two timer outputs, 1SEC pin and CSTo TMR bit, which are derived from the 8 kHz ST-BUS frame pulse F0i. These signals have been implemented to provide the interface controller with a timing ...
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Data Sheet The FE and SE counters will wrap around to 0000 after reaching a terminal count of 1111. When the FE counter wraps around the Framing Error Saturation Indication bit (FSI) will be set, Table 11 on page 14, ...
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MT8926 Bit Name 7-0 CRC CRC Error Counter. This bit counter, which is incremented when the LSB of the MT8976/77 CRC counter toggles. The CRC error counter will wrap around after reaching terminal count (i.e., 11111111 to ...
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Data Sheet Bit Name 7-0 RxBOM Received Bit-Oriented Message. This register contains the eight least significant bits of the ESF bit oriented message codeword. The contents of this register is valid when a bit-oriented message codeword is received by the ...
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MT8926 the BOMV bit of the PMAC Miscellaneous Status Word (Table 5 on page 10, CSTo channel 7 bit 0) will be high. If the next received codeword is not valid, the BOMV bit will become zero and the RxBOM ...
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Data Sheet Bit Name 0 FDLEn Facility Data Link Enable. FDLEn = 1 enables transmission of the facility data link bit- oriented messages on FDLo. The BOM byte is stored in the TxBOM register (Table 13 on page 15, CSTi1 ...
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MT8926 INTA Group 2 SEI* FSI CSI BSI INTERRUPT SOURCES From Snap-shot registers Group 1 RAI ALRM MT8976/77 SYN MT8976/77 Toggle SLIP Detector R Delayed Delay Frame Pulse** Figure 8 - Functional Schematic of Interrupt Mechanism In slave or loop-timed ...
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Data Sheet cleared by INTA ( see Table 11 on page 14). A PMAC interrupting signal is either a low-to-high transition or a change in state (SLIP), therefore, for IRQ to go low the MT8926 must be Armed before the ...
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MT8926 ‡ Signal To Trigger interrupt (IRQ low) SEI SEI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance. FSI FSI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance. CSI CSI ...
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Data Sheet 2.0 Applications Figure 9 on page 21 illustrates a typical application of a MT8926 PMAC. T1 data is transmitted and received using a generic Line Interface Unit (LIU). The LIU passes the received data and extracted clock to ...
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MT8926 IRQ is an open drain interrupt output that will signal the microprocessor when an exception condition occurs (see Figure 8 on page 18). Exception conditions are counter overflows and alarms. Interrupts are reset via the PMAC Control Word of ...
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Data Sheet maximum of 100 msec. This is to accommodate the periodic transmission of message-oriented performance reports. Command and response messages are used to perform various functions, which include the following: 1) line and payload loopback control, 2) protection switch ...
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MT8926 OCTET # SAPI ...
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Data Sheet Absolute Maximum Ratings* Parameter 1 Power Supplies with respect Voltage on any pin other than supplies 3 Current at any pin other than supplies 4 Storage Temperature 5 Continuous Power Dissipation * Exceeding these values ...
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MT8926 AC Electrical Characteristics Parameters 1 Receive Data Setup Time 2 Receive Data Hold Time 3 Extracted Clock Width 4 Extracted 1.5 MHz Clock Period † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are ...
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Data Sheet Channel 2 Bit 1 DATA 2.25V ECLK 0.8V t 2.25V E8Ki 0.8V 2.4 V E8Ko 0 8PD AC Electrical Characteristics Parameters ¿ 1 Clock to Output Delay 2 ST-BUS Setup Time 3 ST-BUS Hold Time ¦ ...
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MT8926 2.25V C2i 0.8V 2.4V CSTo, DSTo 0.4V 2.25V CSTi0/1 0.8V Figure 13 - ST-BUS Timing - CSTo/DSTo Altered by PMAC 2.25V DSTi0/1, CSTi0 0.8V 2.4V DSTo, CSTo 0.4V Figure 14 - T-BUS Timing - CSTo/DSTo Unaltered by PMAC AC ...
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Data Sheet 2.25V C2i 0.8V 2.25V F0i 0.8V t FPH Figure 15 - T-BUS Clock and Frame Pulse Timing AC Electrical Characteristics Parameters 1 1SEC Output Delay † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical ...
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MT8926 Frame n CSTi0 C2i IRQ * INTA Bit. IRQ is returned to High Z by INTA=0, INTA=1 in the previous frames. This can occur in frame n later frame. ** Condition initiating interrupt Note: ...
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Data Sheet Appendix Control and Status Register Summary 7 6 Debounce TSPZCS 1 Disabled 1 Disabled 1 B8ZS 0 Enabled 0 Enabled 0 Jammed Bit Master Control Word 1 (Channel 15, CSTi0) RMLOOP DGLOOP ALL 1’s 1 Enabled 1 Enabled ...
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MT8926 Appendix (continued) Control and Status Register Summary 7 6 UNUSED PMAC Miscellaneous Status Word (Channel 7, CSTo) Cyclic Redundancy Check-6 Error Counter (Channel 11, CSTo) YLALR MIMIC ALRM 1 Detected 1 Detected 1 Detected 0 Normal 0 Not 0 ...
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Data Sheet UNUSED Per Channel Status Word (All Channels on CSTo Except Channels 3, 7, 11, 15, 19, 23, 27, 31) Note 1: In ESF mode: 1: CRC calc. ignored during Sync. 0: CRC checked for Sync. In D3/D4 mode: ...
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MT8926 34 Data Sheet SEMICMF.019 ...
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