MT8926AE Zarlink Semiconductor, MT8926AE Datasheet - Page 16

• Manufacturer Part Number: MT8926AE
• Description: MT8926 - T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

the BOMV bit of the PMAC Miscellaneous Status Word (Table 5 on page 10, CSTo channel 7 bit 0) will be high. If
the next received codeword is not valid, the BOMV bit will become zero and the RxBOM register will retain its most
recent valid message.
The MT8926 will support LAPD message-oriented performance reporting when it is combined with an HDLC
controller such as the MT8952. See Figure 7 on page 17 for FDL operation. The performance monitoring data that
makes up the LAPD message is derived by the combination of MT8976/77 T1 framer and MT8926 PMAC, and is
available on CSTo. This data can then be assembled into a LAPD message and presented to the MT8952 HDLC
controller for transmission over the FDL on a one second basis as per T1.403/408 (see Figure 10 on page 24).
FDLEn of the PMAC Control Word (CSTi1 channel 11 bit 0) must be low to allow transmission of a performance
report from the HDLC controller through pins FDLi and FDLo of the MT8926 to the TxFDL input of the MT8976/77.
The 1SEC output pin or the two second TMR bit of the Miscellaneous Status Word (CSTo channel 7 bit 0) are
derived from the ST-BUS timing and can be used to initiate the transmission of these messages.
MT8926
16
Bit
7
6
5
4
3
2
1
CRCR
Name
BPVR
8KEn
INTA
SER
FSel
FER
SE Counter Reset. Toggling this bit from high to low will reset the severely errored
framing event counter (SE counter, CSTo channel 19 bits 7-4) and event indicator
(SEI bit, CSTo channel 31 bit 4).
FE Counter Reset. Toggling this bit from high to low will reset the framing error
counter (FE counter, CSTo channel 19 bits 3-0) and saturation indicator (FEI bit,
CSTo channel 31 bit 3).
CRC Counter Reset. Toggling this bit from high to low will reset the eight bit CRC
error counter (CRC, CSTo channel 11) and saturation indicator (CSI bit, CSTo
channel 31 bit 2)
BPV Counter Reset. Toggling this bit from high to low will reset the eight bit BPV
counter (BPV, CSTo channel 23) and saturation indicator (BSI bit, CSTo channel 31
bit 1).
Framing Pattern Select. With FSel = 1 and an SF signal detected, both F
errors are considered by the FE and SE counters. The user must set this bit high in
ESF mode.
With FSel = 0 and an SF signal detected, only errors in F
FE and SE counters.
8 KHz Output Enabled. When 8KEn = 1, the E8Ko output will be enabled. That is, the
signal input at E8Ki will be output on E8Ko. See Figure 12 on page 27 for timing.
When 8KEn = 0, the E8Ko output will be high.
Interrupt Acknowledge. When INTA = 1 the MT8926 interrupts are armed or have
been triggered (see Table 15 on page 18). Once INTA is set all interrupting signals
of a group must be inactive before another interrupt of that group can assert the IRQ
output (active low). See Pin Description, pin 20.
When this bit is low the IRQ output state will be high impedance. IRQ will remain in
this state as long as INTA remains low or there are no interrupting events (Table 16
on page 19 Table 17 on page 20).
Table 14 - C Control Word (CSTi1 Channel 11)
Description
T
bits are considered by the
Data Sheet
S
and F
SEMICMF.019
T