MT8926 Zarlink Semiconductor, MT8926 Datasheet
MT8926
Available stocks
Related parts for MT8926
MT8926 Summary of contents
Page 1
This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
Page 2
... SEMICMF.019 ISO-CMOS ST-BUS DS5718 MT8926AE MT8926AP Description The MT8926 Performance Monitoring Adjunct Circuit (PMAC) interworks with Mitel's MT8976/77 and MH89760B to provide performance monitoring data, alarms and T1 maintenance features. It meets the performance monitoring and maintenance requirements of ANSI T1.403 and T1.408, and also supports Channel Service Unit (CSU) requirements ...
Page 3
... MT8926 1 VSS ECLK 2 RxA 3 4 RxB E8Ki E8Ko 7 8 VSS 9 CSTo 10 CSTi0 11 CSTi1 F0i 12 C2i 13 VSS 14 28 PIN PLASTIC DIP 2 28 VDD DSTi1 25 DSTi0 IC E8Ki 24 DSTo E8Ko 23 IC VSS 22 VSS CSTo 21 IC CSTi0 20 IRQ CSTi1 19 1SEC 18 FDLo 17 FLDi 16 RESET ...
Page 4
... V Supply Voltage Input (+5 V RESE RESET Input. Must be high for normal operation. When low, the functions of the MT8926 T will be suspended. 17 FDLi Facility Data Link Input. This input accepts a 4 kbit/sec. facility data link transmit signal, which is routed back out transparently on FDLo if message-oriented signal transmission is enabled (i ...
Page 5
... MT8926 Pin Description Table (continued) Pin # Name 18 FDLo Facility Data Link Output. When bit-oriented messaging is enabled (i.e., PMAC Control Word bit 0, FDLEn, is high), data in the Transmit BOM register will be appended to a 1111 1111 (FF) flag and clocked out of the device at this output. The output timing for this signal is shown in Figure 18 on page 30 ...
Page 6
... ESF payload loopback, as well as the transport of bit-oriented and message-oriented signals over the Facility Data Link (FDL). The control and status data of the MT8926 is transported over spare channels of the existing MT8976/77 ST-BUS streams. Therefore, no new ST-BUS streams are required to upgrade with the PMAC. ...
Page 7
... PMAC - Framer Interworking The MT8926 PMAC is designed to function with the MT8976/77 T1 framer. Figure 9 on page 21 illustrates a typical application and the connections involved in realizing this interface. Both the PMAC and framer receive the extracted clock and data from the T1 line interface. This allows the MT8926 to perform B8ZS recovery and BPV detection, as well ESF synchronization, framing error detection, facility data link extraction, and line loopback code detection ...
Page 8
... Table 1 - Master Status Word 1 Data Substitution Table 2 - Master Status Word 2 Data Substitution The MT8926 can be programmed to either pass data through from FDLi to FDLo and on to the MT8976/77 input TxFDL, or insert bit-oriented messages into the FDL via the transmit bit-oriented message register, channel 7 of CSTi1 ...
Page 9
... PMAC RESET The MT8926 functions may be suspended by making the RESET input low (RESET must be high for normal operation). In the reset state, data entering the PMAC on FDLi, DSTi0 and CSTi0 will pass through unaltered to FDLo, DSTo and CSTo respectively. E8Ko will be high, IRQ will be high impedance and the 1SEC output (and TMR bit) will be low ...
Page 10
... MIMIC MT8976/77 data sheet. 5 ALRM Alarm. This bit will be set if the MT8926 detects the F twelfth frame superframe (alternate yellow alarm indication). ALRM will be low when the F When receiving an ESF signal or if bit 3 (FSEL) of the PMAC Control Word (CSTi1 Channel 11) is low, the ALRM bit will always be low. ...
Page 11
... Loss of Signal Indication (LOS) The LOS bit of Master Status Word 1, Table 3 on page 9, will be high if the MT8926 receives 128 or more consecutive zeros from the T1 interface. LOS will return low when a ones density of 12.5% has been achieved (approximately 48 ones is received in two or less frames). ...
Page 12
... The MT8926 will also detect both framed and un-framed line loopback activate and de-activate codes even in the presence of a BER of 3 errors in 1000 bits. See the PMAC Miscellaneous Status Word, Table 5 on page 10, CSTo channel 7 bit 3 Line Loopback Enable Detect (LLED) and bit 4 Line Loopback Disable Detect (LLDD) ...
Page 13
... Framing Error Event Counters The MT8926 has two four bit counters, the Framing Error Counter (FE) and the Severely Errored Framing Event Counter (SE). The FE counter will be incremented each time a single framing error in the T1 signal is received. The SE counter will be incremented by the reception framing pattern with an error rate that is greater than or equal to two out of six bits ...
Page 14
... BPV and CRC-6 Error Counters The MT8926 has two eight bit counters, the Bipolar Violation Counter (BPV), Table 10 on page 14, and the CRC- 6 Framing Error Counter (CRC), Table 9 on page 14. The BPV counter is incremented each time a non-B8ZS bipolar code violation is received on the T1 interface. The PMAC performs B8ZS recovery of the receive data before BPVs are detected ...
Page 15
... BlAlm, FrCnt These bits (Blue Alarm, Frame Count and External Status) contain information from & Xst the MT8976/77 that is unaltered by the MT8926. See Master Status Word 2 of the MT8976/77 data sheet. 4 SEI Severely Errored Framing Event Indication. This bit goes high when the SE counter is incremented (i ...
Page 16
... AIS is being transmitted in its place. The MT8926 will detect an AIS alarm and indicate its presence by making the AIS bit of Master Status Word 2 (Table 11 on page 14, CSTo channel 31 bit 0) high. This state occurs when the MT8976/77 has lost synchronization and less than three zeros are detected in any 250 microsecond interval ...
Page 17
... FDLEn of the PMAC Control Word (CSTi1 channel 11 bit 0) must be low to allow transmission of a performance report from the HDLC controller through pins FDLi and FDLo of the MT8926 to the TxFDL input of the MT8976/77. The 1SEC output pin or the two second TMR bit of the Miscellaneous Status Word (CSTo channel 7 bit 0) are derived from the ST-BUS timing and can be used to initiate the transmission of these messages ...
Page 18
... FDLo. See Figure 19 on page 30 for timing. Table Control Word (CSTi1 Channel 11) (continued) When the MT8926 is synchronized signal, its receive FDL functions are disabled. BOMV of the PMAC Miscellaneous Status Register and RAI of Master Status Word 1 will be zero. CSTo ...
Page 19
... In the Cleared state (INTA = 0) interrupt sources are ignored and IRQ will always be high impedance. If the interrupts are not being used, then INTA should remain in the Cleared state. When the MT8926 is in the Armed state and an interrupt occurs, it will go to the Triggered state (IRQ = 0). ...
Page 20
... MT8926 must be Armed before the initiating edge occurs. In the case where all interrupts are quiescent and then an interrupt becomes active, while the MT8926 is in its Clear state, IRQ will remain in a high impedance condition. This is true even if the MT8926 is then put in the Armed state and the interrupt persists (see Figure 8 on page 18). ...
Page 21
... MT8926 ‡ Signal To Trigger interrupt (IRQ low) SEI SEI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance. FSI FSI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance. CSI CSI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance ...
Page 22
... C8Kb of the MT8941. In MT8941 normal mode, C8Kb is the reference clock for the ST-BUS and transmit signals (F0, C4 and C2). This 8 kHz output can be turned off (output high) at the MT8926 so the MT8941 reference clock can be derived from another interface. The intrinsic jitter (typical 0.07 UI) and jitter attenuation of the MT8941 will meet T1 ...
Page 23
... MT8926 IRQ is an open drain interrupt output that will signal the microprocessor when an exception condition occurs (see Figure 8 on page 18). Exception conditions are counter overflows and alarms. Interrupts are reset via the PMAC Control Word of the CSTi1 control stream. 2.1 T1.403/408 FDL Message Transfer Overview ANSI standards T1 ...
Page 24
... User defined Operations, Administration and Maintenance (OA&M), terminal-to-network and terminal-to-terminal communications may also pass over the FDL. SEMICMF.019 is gathered, it will take the place of t 0+1 data will move to the t position, the t 0-1 0-2 MT8926 data of the last message. The 0 data will move to the t 0-2 0-3 23 ...
Page 25
... MT8926 OCTET # SAPI ADDRESS 00111000 00111010 00000001 CONTROL 00000011 ONE-SECOND REPORT ...
Page 26
... 0 † - Capacitance ‡ Sym Min Typ Max MT8926 Min Max -0 -0 -40 125 500 ) unless otherwise stated. SS Units Test Conditions Noise margin = 150 Noise margin = 400 mV Units Test Conditions ...
Page 27
... MT8926 AC Electrical Characteristics Parameters 1 Receive Data Setup Time 2 Receive Data Hold Time 3 Extracted Clock Width 4 Extracted 1.5 MHz Clock Period † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are and are for design aid only; not guaranteed and not subject to production testing ...
Page 28
... Figure 12 - 8kHz Extracted Framing Signal † - 2048 kBit/s ST-BUS Streams (Figures 13 and 14) ‡ Sym Min Typ t COD t 15 STS t 50 STH t SOD MT8926 Channel 2 Bit 1 t 8IH Max Units Test Conditions 125 ns 150 pF load 150 pF load CSTo load CSTo ...
Page 29
... MT8926 2.25V C2i 0.8V 2.4V CSTo, DSTo 0.4V 2.25V CSTi0/1 0.8V Figure 13 - ST-BUS Timing - CSTo/DSTo Altered by PMAC 2.25V DSTi0/1, CSTi0 0.8V 2.4V DSTo, CSTo 0.4V Figure 14 - T-BUS Timing - CSTo/DSTo Unaltered by PMAC AC Electrical Characteristics Parameters 1 C2i Clock Period 2 C2i Clock Width High or Low 3 Frame Pulse Setup Time 4 Frame Pulse Width High ...
Page 30
... Typical figures are and are for design aid only; not guaranteed and not subject to production testing 2.25V F0i 0.8V 2.25V C2i 0.8V 2.4V 1SEC 0.4V t 1SD SEMICMF.019 FPS t FPL † - 1SEC Output Timing (Figure 16) ‡ Sym Min Typ Max t 95 1SD t Figure 16 - 1SEC Timing MT8926 t 2W Units Test Conditions ns 150 pF load . 1SD 29 ...
Page 31
... MT8926 Frame n CSTi0 C2i IRQ * INTA Bit. IRQ is returned to High Z by INTA=0, INTA=1 in the previous frames. This can occur in frame n later frame. ** Condition initiating interrupt Note: t (IRQ Output Delay) is dependent on the IRQ pull-up resistor. IOD AC Electrical Characteristics Parameters 1 Data Link Output Delay ...
Page 32
... FSel High-to-Low FPS S T Reset 0 F only T PMAC Control Word (Channel 11, CSTi1) UNUSED A Txt. Sig. Bit Phase Status Word (Channel 3, CSTo) MT8926 2 1 ESFYLW Robbed Bit YLALR 1 Enabled 1 Disabled 1 Enabled 0 Disabled 0 Enabled 0 Disabled SLC-96 CRC/MIMIC Maint. 1 Enabled See Note 1 ...
Page 33
... MT8926 Appendix (continued) Control and Status Register Summary 7 6 UNUSED PMAC Miscellaneous Status Word (Channel 7, CSTo) Cyclic Redundancy Check-6 Error Counter (Channel 11, CSTo) YLALR MIMIC ALRM 1 Detected 1 Detected 1 Detected 0 Normal 0 Not 0 Not Detected Detected Master Status Word 1 (Channel 15, CSTo) SEVERELY ERRORED FRAMING EVENT COUNTER (SE) ...
Page 34
... In ESF mode: 1: CRC calc. ignored during Sync. 0: CRC checked for Sync. In D3/D4 mode: 1: Sync. to first correct S-bit pattern. 0: Will not Sync. if Mimic detected. SEMICMF.019 Rec’d. Sig. Bit Rec’d. Sig. Bit Rec’d. Sig. Bit MT8926 D Rec’d. Sig. Bit 33 ...
Page 35
... MT8926 34 Data Sheet SEMICMF.019 ...
Page 36
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...