MT8926 Zarlink Semiconductor, MT8926 Datasheet - Page 4

• Manufacturer Part Number: MT8926
• Description: T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

SEMICMF.019
Data Sheet
Pin Description Table
Pin #
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
Name
CSTi0 Control ST-BUS Input 0. Accepts the serial ST-BUS stream output on CSTo of the
CSTi1 Control ST-BUS Input 1. Channel 11 of this ST-BUS input stream is used to control specific
RESE
ECLK
CSTo
E8Ko
E8Ki
FDLi
RxA
RxB
V
V
V
V
C2i
F0i
IC
T
SS
SS
SS
DD
System Ground.
Extracted Clock Input. A 1.544 MHz clock derived from the received data. This signal is used
to clock in the data on pins RxA and RxB.
Receive A Input. A unipolar active low signal decoded from the received T1 signal. See
Figure 11 on page 26 for timing information.
Receive B Input. A unipolar active low signal decoded from the received T1 signal. See
Figure 11 on page 26 for timing information.
Internal Connection. Must be tied to V
Extracted 8 kHz Input. A low going pulse on this input is used by the PMAC to locate the
framing bit in the received signal. The device uses this information to detect errors in the
received framing bits. Connect to E8Ko of the MT8976/77. See Figure 12 on page 27 for timing
information.
8 kHz clock output. The 8 kHz signal input at E8Ki is output on this pin when bit 2 (8KEn) of
the PMAC Control Word is set. The output is pulled high when 8KEn is reset. See Figure 12 on
page 27 for timing information.
System Ground.
Control ST-BUS Output. The data that enters the PMAC on CSTi0 will exit the device on this
pin. Data derived by the PMAC will be inserted into specific channels of this output stream. See
Figure 13 on page 28 and Figure 14 on page 28 for timing information and Figure 5 on page 8
for channel allocation.
MT8976/77. The data that enters the PMAC on this pin exits the device on CSTo. The contents
of specific CSTi0 channels is replaced by data derived by the PMAC. See Figure 13 on page 28
and Figure 14 on page 28 for timing information and Figure 4 on page 6 for channel allocation.
features in the device (Table 14 on page 16). Channel 7 is used for the transmit bit-oriented
message (Table 13 on page 15), and channel 15 is used to control loopback functions (Table 4
on page 9). See Figure 13 on page 28 for timing information and Figure 3 on page 5 for
channel allocation.
Frame Pulse Input. This input accepts an 8 kHz signal, which is used to delineate the ST-BUS
frame boundary. See Figure 15 on page 29 for timing information.
2.048 MHz Clock Input. This input accepts a 2.048 MHz clock signal, which is used to clock
ST-BUS control and data streams into and out of the PMAC. See Figure 13 on page 28 and
Figure 14 on page 28 for timing information.
System Ground.
Supply Voltage Input (+5 V).
RESET Input. Must be high for normal operation. When low, the functions of the MT8926
will be suspended.
Facility Data Link Input. This input accepts a 4 kbit/sec. facility data link transmit signal,
which is routed back out transparently on FDLo if message-oriented signal transmission is
enabled (i.e., PMAC Control Word bit 0, FDLEn, is low). This signal is not clocked into the
PMAC. If bit-oriented messaging is enabled (FDLEn high), data on this input will not be
routed to FDLo (see pin 18, FDLo, below).
See Figure 11 on page 26 for timing information.
SS
Description
for normal operation.
MT8926
3