MT8926 Zarlink Semiconductor, MT8926 Datasheet - Page 14

• Manufacturer Part Number: MT8926
• Description: T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

SEMICMF.019
Data Sheet
The FE and SE counters will wrap around to 0000 after reaching a terminal count of 1111. When the FE counter
wraps around the Framing Error Saturation Indication bit (FSI) will be set, Table 11 on page 14, and a G2 interrupt
will be asserted. The Severely Errored Framing Event Indication bit (SEI), Table 11 on page 14, will be set when
the SE counter is incremented. This will also assert a G2 interrupt. These counters are frozen when the PMAC or
MT8976/77 has lost synchronization (i.e., CSTo Channel 7 bit 2, FECV = 0).
The SE and FE counters, as well as the SEI and FSI bits are cleared by a high-to-low transition of bit 7, SE Counter
Reset (SER), and bit 6, FE Counter Reset (FER), of the PMAC Control Word channel 11 CSTi1.
1.11
The MT8926 has two eight bit counters, the Bipolar Violation Counter (BPV), Table 10 on page 14, and the CRC-
6 Framing Error Counter (CRC), Table 9 on page 14. The BPV counter is incremented each time a non-B8ZS
bipolar code violation is received on the T1 interface. The PMAC performs B8ZS recovery of the receive data
before BPVs are detected. The CRC-6 Framing Error Counter is incremented when the least significant bit of the
MT8976/77 CRC error counter is incremented.
The BPV and CRC counters will wrap around to 00000000 after reaching a terminal count of 11111111. When the
BPV counter wraps around the BPV Saturation Indication bit (BSI) will be set, Table 11 on page 14, and a G2
interrupt will be asserted. Similarly, when the CRC counter wraps around the CRC Saturation Indication bit (CSI)
will be set and a G2 interrupt will be asserted.
Bit
7-4
3-0
Table 8 - Framing Error and Severely Errored Framing Event Counters (CSTo Channel 19)
BPV and CRC-6 Error Counters
Name
SE
FE
Severely Errored Framing Event. This four bit counter is incremented when the
MT8926 detects two out of six framing bit errors. It will wrap around after reaching
terminal count and can be reset by toggling bit 7 of the PMAC Control Word
(Table 14 on page 16, CSTi1 channel 11) from high to low.
When receiving a SF T1 signal, both F
PMAC Control Word is set high. If this bit is set low, only errors in the F
counted. When both F
an SF superframe) is not examined for errors because it can be used to indicate a
Yellow alarm.
Framing Error Count. This four bit counter is incremented when a framing bit error is
detected.
When receiving a SF T1 signal, both F
PMAC Control Word is set high. If this bit is set low, only errors in the F
counted. When both F
an SF superframe) is not examined for errors because it can be used to indicate a
Yellow alarm.
The counter shall wrap around after reaching terminal count and can be reset by
toggling bit 6 in the PMAC Control Word (Table 14 on page 16, CSTi1 channel 11)
from high to low.
S
S
and F
and F
T
T
bit errors are counted, F
bit errors are counted, F
Description
S
S
and F
and F
T
T
bit errors are counted if bit 3 in the
bit errors are counted if bit 3 in the
S
S
bit 6 (in the twelfth frame in
bit 6 (in the twelfth frame in
MT8926
T
T
bits will be
bits will be
13