MPC8548E Freescale, MPC8548E Datasheet - Page 65

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MPC8548E

Manufacturer Part Number
MPC8548E
Description
Integrated Processor
Manufacturer
Freescale
Datasheet

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Figure 43
assumes that the DC levels of the clock driver chip is compatible with MPC8548E SerDes reference clock
input’s DC requirement.
Figure 44
Since LVDS clock driver’s common mode voltage is higher than the MPC8548E SerDes reference clock
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
Freescale Semiconductor
HCSL CLK Driver Chip
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Clock Driver
Clock Driver
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
CLK_Out
CLK_Out
CLK_Out
Figure 43
to the fact that clock driver chip's internal structure, output impedance and
termination requirements are different between various clock driver chip
manufacturers, it’s very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the MPC8548E SerDes reference clock receiver requirement
provided in this document.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
through
33 Ω
33 Ω
Figure 46
Clock driver vendor dependent
source termination resistor
100 Ω Differential PWB Trace
below are for conceptual reference only. Due
NOTE
SD_REF_CLK
SD_REF_CLK
50 Ω
High-Speed Serial Interfaces (HSSI)
50 Ω
SerDes Refer.
CLK Receiver
MPC8548E
65

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