MPC8548E Freescale, MPC8548E Datasheet - Page 64

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MPC8548E

Manufacturer Part Number
MPC8548E
Description
Integrated Processor
Manufacturer
Freescale
Datasheet

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High-Speed Serial Interfaces (HSSI)
15.2.3
64
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
HCSL (high-speed current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed (100
to 400 mV) for DC-coupled connection.
Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)
AC-coupled externally. For the best noise performance, the reference of the clock could be DC-
or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as
the clock input (SD_REF_CLK) in use.
Interfacing With Other Differential Signaling Levels
SD_REF_CLK
SD_REF_CLK
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Figure 42. Single-Ended Reference Clock Input DC Requirements
200 mV < Input Amplitude or Differential Peak < 800 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
400 mV < SD_REF_CLK Input Amplitude < 800 mV
100 mV < V
V
0 V
V
max
min
Freescale Semiconductor
< V
> V
V
cm
cm
max
cm
+ 400 mV
– 400 mV
V
< 800 mV
< 400 mV
min
> 0 V
V
cm

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