ADAV803 Analog Devices, ADAV803 Datasheet - Page 35

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

Table 24. Receiver Configuration 1 Register
ADDRESS = 0001001 (0x09)
NOCLOCK
RxCLK1–0
AUTO_DEEM
ERR1–0
L
Table 25. Receiver Co
ADDRESS = 0001010 (0x0A)
RxMUTE
SP_PLL
SP_PLL_SEL1–0
NO
NO_VALIDITY
OCK1–0
NONAUDIO
PH
nfigu
RxMUTE
7
Hard-mutes the audio output for the AES3/SPDIF receiver.
0 = AES3/SPDIF receiver is not muted.
1 = AES3/SPDIF receiver is muted.
AES3/SPDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.
0 = Left/right clock generated from the A
1 = Left/right clock from one of the serial
Selects one of the four serial ports as the
00 = Playback port is selected.
01 = Auxiliary input port is selected.
10 = Record port is selected.
11 = Auxiliary output port is selected.
When the NONAUDIO bit is set, data from the AES3/SPDIF receiv
(SRC). If the NO
the AES3/SPDIF
0 = AES3/SPDIF receiver data is sent to
1 = Data from the AES3/SPDIF receiver i
When the VALIDITY bit is set, data from
0 = AES3/SPDIF receiver data is sent to the SRC.
1 = Data from the AES3/SPDIF receiver is not allowed into the SRC, if the VALIDITY bit is set.
NOCL
7
Selects the source of the receiver clock when the PLL is not locked.
0 = Recovered PLL clock is used.
1 = ICLK1 is used.
Determines the oversampling ratio of the recovered receiver clock.
00 = RxCLK is a 128 × f
01 = RxCLK is a 256 × f
10 = RxCLK is a 512 × f
11 = Reserved.
Automatically de-emphasizes the d
0 = Automatic de-emphasis is disabled.
1 = Automatic de-emphasis is enabled.
Defines what action the receiver
00 = No action is taken.
01 = Last valid sample is held.
10 = Invalid sample is replaced with zeros.
11 = Reserved.
Defines what ac
00 = No action is taken.
01 = Last valid sample is held.
10 = Zeros are sent out after the last valid sample.
11 = Soft-mute of the last valid audio sample.
ration 2 Register
OCK
NAUDIO data is due to DTS, AAC, and so on, as d
tion the receiver should take, if the PLL loses lock.
receiver is not allowed into the SRC regardless of the state of this bit.
SP_PL
6
S
S
S
recovered clock.
recovered clock.
recovered
L
RxCLK1–
6, 5
should take, if the receiver detects a parity or biphase error.
0
SP_PLL_ SEL
5, 4
clock.
ata from the receiver based on the channel status information.
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the SRC.
s not allowed into the SRC, if the NONAUDIO bit is set.
the AES3/SPDIF receiver is not allowed into the SRC.
reference clock to the PLL when SP_PLL is set.
ES3/SPDIF preambles is the reference clock to the PLL.
ports is the reference clock to the PLL.
1–0
AU
4
TO_ DEEMPH
RES
3
efined by the IEC61937 standard, then the data from
er is not allowed into the sample rate converter
RES
2
ERR1–0
3, 2
NO NONAUDIO
1
LOCK1–0
1, 0
NO_VALIDITY
0
ADAV803