ADAV803 Analog Devices, ADAV803 Datasheet - Page 23

no-image

ADAV803

Manufacturer Part Number
ADAV803
Description
Audio Codec
Manufacturer
Analog Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADAV803ASTZ
Manufacturer:
ADI
Quantity:
163
Part Number:
ADAV803ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADAV803ASTZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
SPDIF TRANSMITTER AND RECEIVER
The ADAV803 contains an integrated SPDIF transmitter and
receiver. The transmitter consists of a single output pin,
DITOUT, on which the biphase encoded data appears. The
SPDIF transmitter source can be selected from the different
blocks making up the ADAV803. Additionally, the clock source
for the SPDIF transmitter can be selected from the various clock
sources available in the ADAV803.
The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts
the SPDIF input data stream. The DIRIN pin can be configured
to accept a digital input level, as defined in the Specifications
section, or an input signal with a peak-to-peak level of 200 mV
minimum, as defined by the IEC60958-3 specification. DIR_LF
is a loop filter pin, required by the internal PLL, which is used to
recover the clock from the SPDIF data stream.
The components shown in Figure 42 form a loop filter, which
integrates the current pulses from a charge pump and produces
a voltage that is used to tune the VCO of the clock recovery
PLL. The recovered audio data and audio clock can be routed to
the different blocks of the ADAV803, as required. Figure 39
shows a conceptual diagram of the DIRIN block.
44.1kHz
44.1kHz
48kHz
32kHz
48kHz
32kHz
256
384
256
38
256
512
4
PLL1 MCLK
PLL2 MCLK
REG 0x75
BITS 3–2
REG 0x75
BIT 1
REG 0x75
BIT 5
REG 0x75
BITS 7–6
REG 0x74
BIT 0
Figure 38. PLL Clocking Scheme
REG 0x
REG 0x75
Rev. 0 | Page 23 of 56
BIT 0
BIT 4
×2
×2
75
FS3
FS1
FS2
REG 0x77
REG 0x77
BITS 2–1
BIT 0
÷2
÷2
÷2
AUXILIARY IN
SPDIF
PLAYBACK
Figure 40. Digital Output Transmitter Block Diagram
Figure 41. Digital Input Receiver Block Diagram
ADC
SRC
C*
DIR
PLLINT1
PLLINT1
PLL1
PLL1
* EXTERNAL CAPACITOR IS ONLY REQUIRED
REG 0x63
DIRIN
BITS 2–0
FOR VARIABLE LEVEL SPDIF INPUTS.
LEVEL
DC
DIRIN
DIR
SYSCLK1
SYSCLK2
SYSCLK3
REG 0x74
BIT 4
Figure 39. DIRIN Block
COMPARATOR
DIT
INPUT
DIT
AUDIO
DATA
RECOVERED
CLOCK
RECEIVER
SPDIF
DITOUT
ADAV803

Related parts for ADAV803