ADAV803 Analog Devices, ADAV803 Datasheet - Page 27

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

Table 15. Transmitter User Bit Buffer Size
TxBCONF0
0
1
By using sticky bits and interrupts, the transmit buffers can
notify the host or microcontroller when the first user bit buffer
has been updated and when the second transmit user bit buffer
is full. The sticky bit, TxUBINT, is set when the transmit user bit
buffer has been updated and the second transmit user bit buffer
is ready to accept new user bits. The sticky bit, TxFBINT, is set
whenever the second transmit user bit buffer is full. Any new
writes to this buffer are ignored until the first transmit buffer is
updated. These two bits are located in the interrupt status
register. When the host reads the interrupt status register, these
bits are cleared. Interrupts for the TxUBINT and TxFBINT
sticky bits can be enabled by setting the TxUBMASK and
TxFBMASK bits, respectively, in the interrupt status
mask register.
A
The ADAV803 SPDIF receiver and transmitter sections have an
autobuffering mode allowing the channel status and user bits to
be copied automatically from the receiver to the transmitter
without user intervention. The channel status and user bits can
be independently selected for autobuffering using the
Auto_CSBits and Auto_UBits bits, respectively, in the autobuffer
register. When the receiver and transmitter are running at the
same sample rate, the transmitted channel status and user bits
are the same as the received channel-status and user bits.
In many systems, however, it is likely that the receiver and
transmitter are not running at the same frequency. When the
transmitter sample rate is higher than the receiver sample rate,
the channel status and user bit block is sometimes repeated.
When the transmitter sample rate is lower than the receiver
sample rate, the channel status and user bit blocks might be
dropped. Because the first five bytes of the channel status are
typically constant, they can be repeated or dropped with no
information loss. However, if the PRO bit in the channel status
is set and the local sample address code and time-of-day code
utobuffering
ADDRESS = 0x52
ADDRESS = 0x53
TRANSMITTER USER BIT
TRANSMITTER USER BIT
INDIRECT ADDRESS
DATA REGISTER
REGISTER
Buffer Size
384 bits with Preamble Z as the start of the block.
768 bits with Preamble Z as the start of the block.
Figure 49. Transmitter User Bit Buffer
USER-BIT
BUFFER
16.....23
8.....15
0.....7
SECOND
BUFFER
SPDIF 0
16.....23
8.....15
0.....7
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bytes contain information, these bytes might be repeated or
dropped, in which case information can be lost. It is up to the
user to determine how to handle this case.
When the user bits are transmitted according to the IEC60
format, the messages contained in the user bits can still be
without dropping
is allowed between IUs and messages, zeros can be added or
subtracted to preserve the messages. When the transmitter
sample rate is greater than the receiver sample rate, extra zeros
are stuffed between the messages. When the sample rate of the
transmitter is less than the sample rate of the receiver, the zero
stuffed between the messages are subtracted. If there are not
enough zeros betwe
between IUs are subt
autobuffer register enables the adding or subtracting of zeros
between messages.
Interrupts
The ADAV803 provides interrupt bits to indicate the presence
of certain conditions that require attention. Reading the
interrupt status register allows the user to determine if any of
the interrupts have been asserted. The bits of the interrupt
status register remain high, if set, until the register is read. Two
bits, SRCError and RxError, indicate interrupt conditions in the
sample rate converter and an SPDIF receiver error, respectivel
Both these conditions require a read of the appropriate error
register to determine the exact cause of the inter
E
mask bit in the interrupt status mask register. The interrupt
mask bit m
generated. This feature allows the user to determine which
functions should be responded to.
The dual function pin ZEROL/INT can be set to indicate the
presence of no audio data on the left channel or the presence of
an interrupt set in the interrupt status register. As shown in
Table 16, the function of this pin is selected by the INTRPT bit
in DAC Control Register 4.
Table 16. ZEROL/INT Pin Functionality
INTRPT
0
1
SERIAL DATA PORTS
The ADAV803 contains four flexible serial ports (SPORTs) to
allow data transfer to and from the codec. All four SPORTs are
independent and can be configured as master or slave ports. In
slave mode, the xLRCLK and xBCLK signals are inputs to the
serial ports. In master mode, the serial port generates the
xLRCLK and xBCLK signals. The master clock for the SPORT
can be selected from a number of sources, as shown in
Figure 50.
ach interrupt in the interrupt status register has an associated
ust be set for the corresponding interrupt to be
Pin Functionality
Pin functions as a ZEROL flag pin.
Pin functions as an interrupt pin.
or repeating messages. Because zero-stuffing
en the m
racted as well. The Zero_Stuff_IU bit in the
essages to be subtracted, the zeros
rupt.
ADAV803
sent
958-3
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