ADAV803 Analog Devices, ADAV803 Datasheet - Page 22

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

ADAV803
P
The ADAV803 features a dual PLL configuratio
independent system clocks for asynchronous operation.
Figure 37 shows the block diagram of the PLL section. The PL
generates the internal and system clocks from a 27 MHz cloc
This clock is generated either by a crystal connected between
XIN and XOUT, as shown in Figure 35, or from an external
clock source connected directly to XIN. A 54 MHz clock can
also be used, if the internal clock divider is used.
Both PLLs (PLL1 and PLL2) can be programmed independentl
and can accommodate a range of sampling rates (32/44.1/48
kHz) with selectable system clock oversampling rates of 256 and
384. Higher oversampling rates can also be selected by enabling
the doubling of the sampling rate to give 512 or 768 × f
Note that this option also allows oversampling ratios of 256 o
384 at double sample rates of 64/88.2/96 kHz.
The PLL outputs can b
for the other component blocks such as the ADC, DAC, and so
on. The outputs of the PLLs are also available on the three
SYSCLK pins. Figure 38 shows how the PLLs can be configured
to provide the sampling clocks.
LL SECTION
Figure 35. Crystal Connection
e routed internally t
MCLKO
C
MCLKI
XOUT
XIN
XTAL
C
REG 0x74
BIT 5
÷
2
o act as clock sources
REG 0x74
n to generate
BIT 4
÷2
Figure 37. PLL Section Block Diagram
S
ratios.
REG 0x78
REG 0x78
BIT 6
BIT 7
Rev. 0 | Page 22 of 56
k.
r
L
y
DETECTOR
DETECT
AND LOOP
AND LO
PHASE
PHASE
FILTER
FILTE
R
Table 7. PLL Frequency Selection Options
PLL
1
2A
2B
The PLLs require some external components to operate
correctly. These components, shown in Figure 36, form a loop
filter that integrates the current pulses from a charge pump an
produces a voltage that is used to tune the VCO. Good quali
capacitors, such as PPS fi
a block diagram of the PLL sect n, including master clock
selection. Figure 3
clock output pins, SYSCLK1 to SYSCLK 3, and the intern
clock values, PLL1 and PLL2, are selected.
The clock nodes, PLL1 and PLL2, can be used as master c
for the other blocks in the ADAV803 such as the DAC or ADC.
The PLL has separate supply and ground pins, which sh
as clean as possible to prevent electrical noise from being
converted into clock jitter by coupling onto the loop
OP
OR
PLL_LF1
PLL_LF2
Sample Rate (f
32/44.1/48 kHz
32/44.1/48 kHz
64/88.2/96 kHz
64/88.2/96 kHz
Same as f
For PLL 2A
÷N
÷N
VCO
VCO
6.8nF
S
AVDD
selected
SCALER N1
SCALER N2
SCALER N3
8 shows how the clock freque
OUTPUT
OUTPUT
OUTPUT
Figure 36. PLL Loop Filter
S
)
PLL1
PLL2
3.3Ω
100nF
lm, are recommended. Figure 37 shows
Normal f
256/384 × f
256/384 × f
512 × f
512 × f
SYSCLK1
SYSCLK2
SYSCLK3
PLL_LFx
io
PLL BLOCK
S
S
MCLK Selection
S
S
S
ncies at the
Double f
512/768 × f
256/384 × f
512/768 × f
256/384 × f
filter pins.
ould be
al PLL
locks
S
ty
S
S
S
S
d