WM8955BL Wolfson Microelectronics, WM8955BL Datasheet - Page 14
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WM8955BL
Manufacturer Part Number
WM8955BL
Description
Stereo DAC
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8955BL.pdf
(44 pages)
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w
WM8955BL
CONTROL INTERFACE TIMING – 2-WIRE MODE
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DBVDD = 3.3V, DGND = 0V, T
PARAMETER
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
Test Conditions
DBVDD = 3.3V, DGND = 0V, T
PARAMETER
Program Register Input Information
SCLK Frequency
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
Pulse width of spikes that will be suppressed
SCLK
SDIN
t
3
A
A
t
1
= +25
= +25
t
6
o
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
t
9
t
2
t
7
SYMBOL
t
SYMBOL
5
t
t
t
t
t
t
t
t
t
SCH
DSU
DHO
CSH
SCS
SCY
SCL
CSL
CSS
t
ps
t
t
t
t
t
t
t
t
t
t
ps
1
2
3
4
5
6
7
8
9
t
4
t
500
200
600
600
600
100
600
MIN
MIN
3
1.3
80
80
40
40
40
40
40
0
0
0
TYP
TYP
PD Rev 4.1 February 2007
MAX
MAX
526
300
300
900
5
5
Production Data
t
8
UNIT
UNIT
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
14