WM8955BL Wolfson Microelectronics, WM8955BL Datasheet - Page 13
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WM8955BL
Manufacturer Part Number
WM8955BL
Description
Stereo DAC
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8955BL.pdf
(44 pages)
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Production Data
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)
CONTROL INTERFACE TIMING – 3-WIRE MODE
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DBVDD = 3.3V, DGND = 0V, T
PARAMETER
System Clock Timing Information
DACLRC propagation delay from BCLK falling
edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
Test Conditions
DBVDD = 3.3V, DGND = 0V, T
PARAMETER
System Clock Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
DACLRC setup time to BCLK rising edge
DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
DACLRC
DACDAT
SCLK
SDIN
CSB
BCLK
A
A
= +25
= +25
t
BCH
o
o
C, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
C, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
t
BCY
t
DSU
t
SCH
t
DHO
t
t
BCL
DS
t
SCY
t
SYMBOL
t
SCL
CSL
SYMBOL
t
t
t
t
t
LRSU
t
BCY
BCH
LRH
BCL
DH
t
t
t
DHT
DST
DL
t
LRH
t
LSB
LRSU
MIN
MIN
10
10
50
20
20
10
10
10
t
SCS
TYP
TYP
t
CSS
PD Rev 4.1 February 2007
t
CSH
MAX
MAX
10
WM8955BL
UNIT
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
13