WM8955BL Wolfson Microelectronics, WM8955BL Datasheet
WM8955BL
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WM8955BL Summary of contents
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... Stereo DAC For Portable Audio Applications DESCRIPTION The WM8955BL is a low power, high quality stereo DAC with integrated headphone and earpiece amplifiers, designed to reduce external component requirements in portable digital audio applications. The on-chip headphone amplifiers can deliver 40mW into a 16Ω ...
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... WM8955BL DESCRIPTION....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION.................................................................................. 3 PIN DESCRIPTION................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 TERMINOLOGY ............................................................................................................... 7 OUTPUT PGA’S LINEARITY ........................................................................................... 8 HEADPHONE OUTPUT THD VERSUS POWER ............................................................ 9 POWER CONSUMPTION .............................................................................................. 10 AUDIO PATHS OVERVIEW ................................................................................ 11 SIGNAL TIMING REQUIREMENTS .................................................................... 12 SYSTEM CLOCK TIMING.............................................................................................. 12 AUDIO INTERFACE TIMING – ...
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... WM8955BLGECO/RV -25°C to +85°C Note: Reel quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY LEVEL 28-lead COL QFN MSL3 (4x4x0.75mm) (Pb-free) 28-lead COL QFN MSL3 (4x4x0.75mm) (Pb-free, tape and reel) WM8955BL PEAK SOLDERING TEMPERATURE 260°C 260°C PD Rev 4.1 February 2007 3 ...
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... WM8955BL PIN DESCRIPTION PIN NO NAME 1 MCLK Digital Input 2 DCVDD 3 DBVDD 4 DGND Digital Input / Output 5 BCLK Digital Input 6 DACDAT 7 DACLRC Digital Input / Output 8 PLLGND 9 MONOOUT Analogue Output 10 OUT3 Analogue Output 11 ROUT1 Analogue Output Analogue Output 12 LOUT1 13 HPGND 14 ROUT2 Analogue Output 15 LOUT2 Analogue Output ...
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... Analogue supplies range AVDD, HPVDD Ground DGND, AGND, HPGND Notes 1. The DCVDD voltage must be lower than or equal to the DBVDD voltage. w -0.3V DGND -0.3V AGND -0.3V -25°C -65°C TEST CONDITIONS DCVDD 1.42 DBVDD 1.71 WM8955BL MIN MAX +4.5V DBVDD +0.3V AVDD +0.3V +85°C +150°C MIN TYP MAX UNIT 3.6 V 3.6 V 1.8 3.6 V ...
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... WM8955BL ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.5V, AVDD = HPVDD = 3.3V, T PARAMETER SYMBOL DAC to Line-Out (10kΩ / 50pF load) Signal to Noise Ratio SNR (A-weighted) Total Harmonic Distortion THD Channel Separation Analogue Mixer Inputs (LINEINL/R to L/ROUT1 with 10kΩ / 50pF load) Full-scale Input Signal Level ...
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... Normally measured by sending a full scale signal down one channel and measuring the other +25 C, 1kHz signal 48kHz, 24-bit audio data unless otherwise stated. A TEST CONDITIONS MIN –3% –3% 0.7×DBVDD -1mA 0.9×DBVDD 1mA OL WM8955BL TYP MAX UNIT AVDD/2 +3% V AVDD/2 + 0.3×DBVDD V V 0.1×DBVDD V PD Rev 4.1 February 2007 7 ...
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... WM8955BL OUTPUT PGA’S LINEARITY 10 0 Output PGA Gains -10 -20 -30 -40 -50 -60 - 1.75 Output PGA Gain Step Size 1.5 1.25 1 0.75 0.5 0. 100 XXXVOL Register Setting [binary 100 XXXVOL Register Setting [binary] Production Data MONOOUT ROUT1 LOUT1 ROUT2 LOUT2 ...
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... HEADPHONE OUTPUT THD VERSUS POWER 0 Headphone Power vs THD+N (16 Ohm load) -20 -40 -60 -80 -100 Headphone Power vs THD+N (32 Ohm load) -20 -40 -60 -80 -100 Power [mW Power [mW] WM8955BL AVDD=3.3V AVDD=2.5V AVDD=1.8V 60 AVDD=3.3V AVDD=2.5V AVDD=1. Rev 4.1 February 2007 9 ...
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... WM8955BL POWER CONSUMPTION The power consumption of the WM8955BL depends on the following factors. • Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings. • Operating mode: Power consumption is lower in mono modes than in stereo, as one DAC is switched OFF. Unused analogue outputs should be switched off ...
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... Production Data AUDIO PATHS OVERVIEW w WM8955BL PD Rev 4.1 February 2007 11 ...
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... WM8955BL SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2 = 0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low ...
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... BCY LRSU DS LRH SYMBOL t BCY t BCH t BCL t LRSU t LRH CSL t SCY t t SCH SCL LSB t t DSU DHO WM8955BL MIN TYP MAX UNIT MIN TYP MAX UNIT CSH t CSS t SCS PD Rev 4 ...
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... WM8955BL Test Conditions o DBVDD = 3.3V, DGND = 0V +25 C, Slave Mode 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. A PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time ...
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... T1 Figure 6 Internal Power on Reset Circuit Schematic The WM8955BL includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to reset the digital logic into a default state after power up. The power on reset circuit is powered from DCVDD and monitors DCVDD and AVDD. It asserts PORB low if DCVDD or AVDD are below a minimum threshold ...
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... GSM, CDMA and PDC phones and other portable systems. To allow full software control over all its features, the WM8955BL offers a choice wire MPU control interface fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs ...
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... Production Data DIGITAL VOLUME CONTROL The WM8955BL has on-chip digital attenuation from –127dB to 0dB in 0.5dB steps, allowing the user to adjust the volume of each channel separately. The level of attenuation for an eight-bit code X is given by: -0.5 × (255 – for 1 ≤ X ≤ 255; ...
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... WM8955BL TONE CONTROL The WM8955BL provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take two different forms: • Linear bass control: bass signals are amplified or attenuated by a user programmable gain ...
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... The WM8955BL also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. This function is enabled by default. To play back an audio signal, the WM8955BL must first be unmuted by setting the DACMU bit to zero. ...
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... WM8955BL LINE INPUTS AND OUTPUT MIXERS The WM8955BL provides the option to mix the DAC output signal with analogue line-in signals from the LINEINL, LINEINR and MONOIN+ and MONOIN- pins. The level of the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers). ...
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... RD2MO 0 Right DAC to Mono Mixer 0 = Disable (Mute Enable Path 7 RI2MO 0 LINEINR Signal to Mono Mixer 0 = Disable (Mute Enable Path 6:4 RI2MOVOL 101 LINEINR Signal to Mono Mixer Volume (-9dB) 000 = 0dB … (3dB steps) 111 = -21dB WM8955BL DESCRIPTION DESCRIPTION PD Rev 4.1 February 2007 21 ...
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... WM8955BL DIFFERENTIAL MONO LINE-IN The WM8955BL can take either a single-ended or a differential mono signal and mix it into the LOUT1/2 and ROUT1/2 outputs. In both cases, LINEINL and LINEINR still remain available as stereo line-in. Differential mono input mode is enabled by setting the DMEN bit, as shown below. ...
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... All outputs are disabled by default. To save power, unused outputs should remain disabled. Outputs can be enabled at any time, except when the WM8955BL is in OFF mode, as this may cause pop noise (see Minimising Pop Noise at the Analogue Outputs) ...
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... WM8955BL LOUT1/ROUT1 OUTPUTS The LOUT1 and ROUT1 pins can drive a 16Ω or 32Ω headphone or a line output (see Headphone Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL, respectively ...
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... Analogue MUTE 7 MOZC 0 MONOOUT zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately 0 TOEN 1 as for LOUT1 / ROUT1 BIT LABEL DEFAULT 8:7 OUT3SW 00 OUT3 select 00 : VREF 01 : ROUT1 10 : MONOOUT 11 : right mixer output WM8955BL DESCRIPTION DESCRIPTION DESCRIPTION PD Rev 4.1 February 2007 25 ...
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... Electrical Characteristic section for timing information. MASTER AND SLAVE MODE OPERATION The WM8955BL can be configured as either a master or slave mode device master device the WM8955BL generates BCLK and DACLRC and thus controls sequencing of the data transfer on DACDAT. In slave mode, the WM8955BL responds with data to clocks it receives over the digital audio interface ...
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... Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. Figure 15 DSP Mode Audio Interface (Mode A; LRP = Justified Audio Interface (assuming n-bit word length) WM8955BL PD Rev 4.1 February 2007 27 ...
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... WM8955BL Figure 16 DSP Mode Audio Interface (Mode B; LRP = 1) AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below. REGISTER ADDRESS R7 (07h) Digital Audio Interface Format Table 18 Audio Data Format Control Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual word length will be 24 bits ...
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... Production Data MASTER CLOCK AND PHASE LOCKED LOOP The WM8955BL has an on-chip phase-locked loop (PLL) circuit that can be used to: • generate a master clock for the WM8955BL audio function from another external clock, e.g. in telecoms applications. The PLL circuit is shown below. MCLK DIV2 ...
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... WM8955BL The PLL frequency ratio (2Eh int ( int (2 (R-N)) Example: MCLK = 12MHz required clock = 12.288MHz R should be chosen to ensure 5<N<13. There is a divide by 4 and selectable divide by 2 after the PLL which should be set to meet this requirement. Enabling the divide by 2 sets the required f 12 ...
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... With BCLKDIV2=1, the LRCLK output produces a non-50:50 duty cycle if BCLK/LRCLK is not an even integer. The clocking of the WM8955BL is controlled using the MCLKDIV2, USB, and SR control bits. Setting the MCLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode ...
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... WM8955BL MCLK MCLK DAC SAMPLE RATE MCLKDIV2=0 MCLKDIV2=1 ‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8711 and WM8721) 12.288MHz 24.576MHz 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 11.2896MHz 22.5792MHz 8.0182 kHz (MCLK/1408) 11 ...
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... Once the WM8955BL has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8955BL register address plus the first bit of register data). The WM8955BL then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i ...
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... WM8955BL Figure 19 2-Wire Serial Control Interface The WM8955BL has two possible device addresses, which can be selected using the CSB pin. CSB STATE Low High Table 25 2-Wire MPU Interface Address Selection POWER SUPPLIES The WM8955BL can use up to four separate power supplies: • ...
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... Production Data POWER MANAGEMENT The WM8955BL has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To avoid any pop or click noise important to enable or disable functions in the correct order (see Applications Information) ...
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... Table 28 Oversampling Rate Selection SAVING POWER AT LOW SUPPLY VOLTAGES The analogue supplies to the WM8955BL can run from 1.8V to 3.6V. By default, all analogue circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1.8V. However, at lower voltages possible to save power by reducing the internal bias currents used in the analogue circuitry ...
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... LI2MO LI2MOVOL RD2MO RI2MO RI2MOVOL LO2VU LO2ZC RO2VU RO2ZC 0 MOZC 0 0 PLLOUT PLL_RB DIV2 [17:9] K [8:0] 0 KEN WM8955BL BIT3 BIT2 BIT1 BIT0 LOUT1VOL ROUT1VOL DACMU DEEMPH 0 WL FORMAT SR USB BASS (Bass Intensity) TRBL (Treble Intensity DACINV TOEN DACOSR 0 ...
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... WM8955BL DIGITAL FILTER CHARACTERISTICS Depending on the MCLK frequency and sample rate selected, 4 different types of digital filter can be used in the DAC, called Type and 3 (see “Master Clock and Audio Sample Rates”). The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the following pages ...
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... Frequency (Fs) Figure 26 DAC Filter Frequency Response – Type 3 w 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 0 0.05 0.1 0.15 0.2 2.5 3 Figure 23 DAC Filter Ripple – Type 1 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 0 0.05 0.1 2.5 3 Figure 25 DAC Filter Ripple – Type 2 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 0.05 0.1 2.5 3 Figure 27 DAC Filter Ripple – Type 3 WM8955BL 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (Fs) 0.15 0.2 0.25 Frequency (Fs) 0.15 0.2 0.25 Frequency (Fs) PD Rev 4.1 February 2007 39 ...
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... WM8955BL APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 28 Recommended External Component Diagram w Production Data PD Rev 4.1 February 2007 40 ...
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... To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER UP • Switch on power supplies. By default the WM8955BL is in OFF Mode (i.e. only the control interface is powered up) • Enable the reference voltage VREF by setting the WM8955BL to Standby mode. DO NOT enable any of the analogue outputs at this point. • ...
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... EARPIECE OUTPUT CONFIGURATION LOUT2 and ROUT2 can differentially drive a mono 32Ω earpiece as shown below. WM8955BL ROUT2INV = 1 Figure 31 Earpiece Output Connection The right channel is inverted by setting the ROUT2INV bit, so that the signal across the earpiece is the sum of left and right channels ...
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... BODY, 0.45 mm LEAD PITCH X X DETAIL 1 4 INDEX AREA (D/2 X E/2) SEE DETAIL 2 aaa aaa TOP VIEW ccc C DETAIL 1 A PIN 1 5 0.08 C 0.275MM IDENTIFICATION 0.150MM SQUARE 0.275MM G NOTE 1 7 WM8955BL DM043 DETAIL Datum Terminal tip e Rev 4.1 February 2007 43 ...
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... WM8955BL IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...