ADSP-21060 Analog Devices, ADSP-21060 Datasheet - Page 18

• Manufacturer Part Number: ADSP-21060
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Parameter
Clock Input
Timing Requirements:
t
t
t
t
Parameter
Reset
Timing Requirements:
t
t
NOTES
1
2
Parameter
Interrupts
Timing Requirements:
t
t
t
NOTES
1
2
CK
CKL
CKH
CKRF
WRST
SRST
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET
is low, assuming stable V
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
SIR
HIR
IPW
Only required for IRQx recognition in the following cycle.
Applies only if t
ADSP-21060/ADSP-21060L
SIR
and t
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
RESET Pulsewidth Low
RESET Setup before CLKIN High
IRQ2-0 Setup before CLKIN High
IRQ2-0 Hold before CLKIN High
IRQ2-0 Pulsewidth
HIR
DD
requirements are not met.
and CLKIN (not including start-up time of external clock oscillator).
RESET
CLKIN
2
IRQ2-0
CLKIN
CLKIN
1
1
1
2
Min
25
7
5
40 MHz
t
CKH
4t
14 + DT/2
18 + 3DT/4
2 + t
Min
Min
t
IPW
ADSP-21060
CK
Max
100
3
t
CK
ADSP-21060
WRST
ADSP-21060
t
t
CK
SIR
Min
30
7
5
t
HIR
t
Max
t
Max
12 + 3DT/4
33 MHz
CKL
CK
Max
100
3
t
SRST
Min
25
8.75
5
Min
4t
14 + DT/2
Min
18 + 3DT/4
2 + t
40 MHz
CK
CK
ADSP-21060L
ADSP-21060L
ADSP-21060L
Max
100
3
Max
t
Max
12 + 3DT/4
CK
Min
30
8.75
5
33 MHz
Max
100
3
Units
ns
ns
Units
ns
ns
ns
Units
ns
ns
ns
ns