MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 93

• Manufacturer Part Number: MCIMX35
• Manufacturer: Motorola Semiconductor Products

1
The parallel ATA module interface consists of a total of 29 pins. Some pins act on different function in
different transfer mode. There are various requirements for timing relationships among the function pins,
in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA
module registers.
4.7.17.1
Table 60
4.7.17.2
This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification.
The user needs to use level shifters for 3.3-V or 5.0-V compatibility on the ATA interface.
The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast
UDMA mode operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Few vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When it is high, the bus
should drive from host to device. When it is low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state buses is always avoided.
Freescale Semiconductor
SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with
all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value.
SI1
SI2
SI3
ID
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
ATA Interface Signals
Rising edge slew rate for any signal on the ATA
interface
Falling edge slew rate for any signal on the ATA
interface
Host interface signal capacitance at the host
connector
and
General Timing Requirements
Figure 65
ATA Electrical Specifications (ATA Bus, Bus Buffers)
1
1
PARAMETER
define the AC characteristics of the interface signals on all data transfer modes.
Table 60. AC Characteristics of All Interface Signals
Figure 65. ATA Interface Signals Timing Diagram
Preliminary—Subject to Change Without Notice
SI2
SYMBOL
S
S
C
rise
fall
host
1
1
SI1
Min.
—
—
—
Max.
1.25
1.25
20
UNIT
V/ns
V/ns
pF
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