MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 16

• Manufacturer Part Number: MCIMX35
• Manufacturer: Motorola Semiconductor Products

4.3
Any i.MX35 board design must comply with the power-up and power-down sequence guidelines as
described in this section to guarantee reliable operation of the device. Any deviation from these sequences
can result in any or all of the following situations:
4.3.1
The Power-up sequence should be completed as follows:
4.3.2
The power-up in reverse order is recommended. However, all power supplies can be shut down at the same
time.
16
Static
Note: Typical column: TA = 25°C
Note: Maximum column TA = 70°C
Power
Mode
•
•
•
1. Assert Power on Reset (POR).
2. Turn on digital logic domain and I/O power supplies VDDn and NVCCx.
3. Turn on all other analog power supplies, including PHY1_VDDA, USBPHY1_VDDA_BIAS,
4. Negate the POR signal.
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
Excessive current during power-up phase
Prevent the device from booting
Irreversible damage to the i.MX35 processor (worst-case scenario)
PHY2_VDD, USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD,
and FUSEVDD. (FUSEVDD is tied to GND if fuses are not being programmed).
QVCC1,2,3,4 = 1.0v
.Arm is in wait for interrupt mode.
.MAX is halted
.L2 cache is kept powered.
.L2 cache control logic off.
.AWB enabled.
.MCU PLL is off.
.PER PLL is off.
.All clocks are gated off.
.OSC 24MHz is off
.OSC audio is off
.RNGC internal osc is off
Supply Power-Up/Power-Down Requirements and Restrictions
Powering Up
Powering Down
Description
Table 10. MCIMX35 Power Modes (continued)
Preliminary—Subject to Change Without Notice
770
Typ.
QVCC(ARM/L2
Peripheral)
µA
Max.
TBD
50
Typ.
MVDD/PVDD
µA
Max.
TBD
Freescale Semiconductor
OSC_AUDO_VDD
26
Typ.
OSC24M_VDD
µA
Max.
TBD