MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 15

• Manufacturer Part Number: MCIMX35
• Manufacturer: Motorola Semiconductor Products

4.2
Table 10
Freescale Semiconductor
Wait
Doze
Stop
Power
Mode
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
provides descriptions of the power modes of the MCIMX35 processor.
QVCC1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is active.
L2 cache is kept powered.
MCU PLL is on (400 MHz)
PER PLL is off (can be configured)
(default: 300 MHz)
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured).
.RNGC internal osc is off
QVCC1,2,3,4 = 1.1v (min.)
ARM is in wait for interrupt mode.
MAX is halted.
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is on(400 MHz)
PER PLL is off (can be configured).
(300Mhz).
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured)
.RNGC internal osc is off
QVCC1,2,3,4 = 1.1v (min.)
.Arm is in wait for interrupt mode.
.MAX is halted
.L2 cache is kept powered.
.L2 cache control logic off.
.AWB enabled.
.MCU PLL is off.
.PER PLL is off.
.All clocks are gated off.
.OSC 24MHz is on
.OSC audio is off
.RNGC internal osc is off
Power Modes
Description
Preliminary—Subject to Change Without Notice
Table 10. MCIMX35 Power Modes
790
Typ.
TBD
TBD
QVCC(ARM/L2
Peripheral)
µA
Max.
TBD
TBD
TBD
40
Typ.
TBD
TBD
MVDD/PVDD
µA
Max.
TBD
TBD
TBD
OSC_AUDO_VDD
1
TBD
TBD
Typ.
OSC24M_VDD
mA
Max.
TBD
TBD
TBD
15