WM8978_06 Wolfson Microelectronics Ltd., WM8978_06 Datasheet - Page 67

• Manufacturer Part Number: WM8978_06
• Description: Stereo Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

Pre-Production
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Table 44 Speaker Boost Stage Control
Table 45 Output Boost Stage Details
Table 46 AUXR – ROUT2 BEEP Mixer Function
ZERO CROSS TIMEOUT
Table 47 Timeout Clock Enable Control
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output
PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This
is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital
and is equal to 2
R49
Output control
R1
Power
management
1
R43
Beep control
R7
Additional
Control
SPKBOOST
REGISTER
REGISTER
ADDRESS
ADDRESS
REGISTER
ADDRESS
0
1
21
2
8
5
4
3:1
0
* input clock period.
0
BIT
STAGE GAIN
BIT
BIT
1.5x (3.52dB)
OUTPUT
1x (0dB)
SPKBOOST
BUFDCOPEN
MUTERPGA2INV
INVROUT2
BEEPVOL
BEEPEN
SLOWCLKEN
LABEL
LABEL
LABEL
OUTPUT DC
1.5xAVDD/2
AVDD/2
LEVEL
0
DEFAULT
DEFAULT
DEFAULT
000
0
0
0
0
0
CONFIGURATION
OUTPUT STAGE
Non-inverting
Slow clock enable. Used for both the
jack insert detect debounce circuit and
the zero cross timeout.
0 = slow clock disabled
1 = slow clock enabled
Inverting
0 = speaker gain = -1;
1 = speaker gain = +1.5;
Dedicated buffer for DC level shifting
output stages when in 1.5x gain
boost configuration.
0=Buffer disabled
1=Buffer enabled (required for 1.5x
gain boost)
Mute input to INVROUT2 mixer
000 = -15dB
...
111 = +6dB
1 = enable AUXR beep input
Invert ROUT2 output
AUXR input to ROUT2 inverter gain
0 = mute AUXR beep input
DC = AVDD / 2
DC = 1.5 x AVDD / 2
DESCRIPTION
DESCRIPTION
DESCRIPTION
PP Rev 3.0 May 2006
WM8978
67