WM8978_06 Wolfson Microelectronics Ltd., WM8978_06 Datasheet - Page 35

• Manufacturer Part Number: WM8978_06
• Description: Stereo Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

Pre-Production
Figure 18 ADC Digital Filter Path
w
Table 14 ADC Enable Control
Table 15 ADC Control
SELECTABLE HIGH PASS FILTER
The ADCs are enabled by the ADCENL/R register bit.
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit.
ADCOSR register bit.
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two
modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off
frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off
frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown
in Table 17.
R2
Power
management 2
R14
ADC Control
REGISTER
REGISTER
ADDRESS
ADDRESS
0
1
0
1
3
BIT
BIT
With ADCOSR=0 the oversample rate is 64x which gives lowest power
ADCENL
ADCENR
ADCLPOL
ADCRPOL
ADCOSR
LABEL
LABEL
The oversampling rate of the ADC can be adjusted using the
0
0
DEFAULT
0
0
0
DEFAULT
Enable ADC left channel:
0 = ADC disabled
1 = ADC enabled
Enable ADC right channel:
0 = ADC disabled
1 = ADC enabled
ADC left channel polarity adjust:
0=normal
1=inverted
ADC right channel polarity adjust:
0=normal
1=inverted
0=64x (lower power)
1=128x (best performance)
ADC oversample rate select:
DESCRIPTION
DESCRIPTION
PP Rev 3.0 May 2006
WM8978
35