WM8978 Wolfson Microelectronics Ltd., WM8978 Datasheet - Page 82

no-image

WM8978

Manufacturer Part Number
WM8978
Description
The WM8978 is a low power, high quality stereo codec designed for portable applications such as Digital still camera or Digital Camcorde
Manufacturer
Wolfson Microelectronics Ltd.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM8978CGEFL/RV
Manufacturer:
WOLFSON
Quantity:
10 000
Part Number:
WM8978CGEFL/RV
Manufacturer:
WOLFSON
Quantity:
20 000
Part Number:
WM8978CGEFL/RV
0
Part Number:
WM8978G
Manufacturer:
SANYO
Quantity:
87 018
Part Number:
WM8978G
Manufacturer:
WM
Quantity:
20 000
Part Number:
WM8978G
Manufacturer:
WOLFSON
Quantity:
270
Part Number:
WM8978GEFL
Manufacturer:
WOLFSON
Quantity:
20 000
Part Number:
WM8978GEFL/RV
Manufacturer:
WOLFSON
Quantity:
9 870
Part Number:
WM8978GEFL/RV
Manufacturer:
WM
Quantity:
1 000
WM8978
REGISTER BITS BY ADDRESS
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as "Reserved" should not be changed from the default.
w
0 (00h)
1 (01h)
2 (02h)
REGISTER
ADDRESS
[8:0]
8
7
6
5
4
3
2
1:0
8
7
6
5
4
3
BIT
RESET
BUFDCOPEN
OUT4MIXEN
OUT3MIXEN
PLLEN
MICBEN
BIASEN
BUFIOEN
VMIDSEL
ROUT1EN
LOUT1EN
SLEEP
BOOSTENR
BOOSTENL
INPPGAENR
LABEL
N/A
0
0
0
0
0
0
0
00
0
0
0
0
0
0
DEFAULT
Software reset
Dedicated buffer for DC level shifting output
stages when in 1.5x gain boost configuration.
0=Buffer disabled
1=Buffer enabled (required for 1.5x gain boost)
OUT4 mixer enable
0=disabled
1=enabled
OUT3 mixer enable
0=disabled
1=enabled
PLL enable
0=PLL off
1=PLL on
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Analogue amplifier bias control
0=disabled
1=enabled
Unused input/output tie off buffer enable
0=disabled
1=enabled
Reference string impedance to VMID pin
00=off (open circuit)
01=75kΩ
10=300kΩ
11=5kΩ
ROUT1 output enable
0=disabled
1=enabled
LOUT1 output enable
0=disabled
1=enabled
0 = normal device operation
1 = residual current reduced in device standby
mode
Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Right channel input PGA enable
0 = disabled
1 = enabled
DESCRIPTION
PTD Rev 2.6 November 2005
Preliminary Technical Data
Resetting the
Chip
Analogue
Outputs
Power
Management
Power
Management
Master Clock
and Phase
Locked Loop
(PLL)
Input Signal
Path
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
REFER TO
82

Related parts for WM8978