WM8978 Wolfson Microelectronics Ltd., WM8978 Datasheet - Page 69

• Manufacturer Part Number: WM8978
• Description: The WM8978 is a low power, high quality stereo codec designed for portable applications such as Digital still camera or Digital Camcorde
• Manufacturer: Wolfson Microelectronics Ltd.

Preliminary Technical Data
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Table 50 Clock Control
LOOPBACK
COMPANDING
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
The WM8978 supports A-law and -law and companding and linear mode on both transmit (ADC)
and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by
writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
R6
Clock
Generation
Control
REGISTER
ADDRESS
0
4:2
7:5
8
BIT
MS
BCLKDIV
MCLKDIV
CLKSEL
LABEL
0
000
010
1
DEFAULT
Sets the chip to be master over LRC
and BCLK
0=BCLK and LRC clock are inputs
1=BCLK and LRC clock are outputs
generated by the WM8978 (MASTER)
Configures the BCLK output frequency,
for use when the chip is master over
BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
PTD Rev 2.6 November 2005
DESCRIPTION
WM8978
69