HFC-U Cologne Chip AG, HFC-U Datasheet - Page 34

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

All processor modes:
Reading STATUS_DISBUSY register delays the transition from nobusy to busy until any other
register of the HFC-U is accessed (see Figure 5 on page 26).
This register should be checked for nobusy before accessing any busy-critical register to avoid a
transition from nobusy to busy during a FIFO register access, which may destroy register values.
Busy-critical register are all FIFO registers, the B-channel data register B1_D, B2_D and D_D of the
GCI/IOM bus part.
ISA-PC mode:
It is possible to read the STATUS_DISBUSY register in ISA-PC mode directly by a READ
operation to the port address with SA0='1', but it is necessary to enable the HFC-U going into busy
cycle again after a data port access with SA0='0'.
March 1997
Name
STATUS
Reading the STATUS register clears no bit.
STATUS_DISBUSY
(1Ch)
Bits
0
1
2
3
4
5
6
7
r/w
r
r
r
r
r
r
r
r
(1Dh)
Function
BUSY/NOBUSY status
'1'
'0'
unused, '0'
BUSY/NOBUSY transition interrupt status
'1'
GCI I-change interrupt
'1'
timer status
'0'
'1'
receiver ready (RxR) of monitor channel
'1'
FRAME interrupt has occured (any data channel interrupt)
all masked D-channel and B-channel interrupts are "ored"
ANY interrupt
all masked interrupts are "ored"
r
All bits are the same as in the STATUS register.
the HFC-U is in BUSY state
the HFC-U is in NOBUSY state, access on all FIFO
functions is now possible
the HFC-U has changed from BUSY to NOBUSY
state, access on all FIFO functions is now possible
This bit is reset by a read of INT_S1.
a different I-value on GCI was detected
timer not elapsed
timer elapsed
2 monitor bytes have been received
see STATUS register
HFC-U
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