HFC-U Cologne Chip AG, HFC-U Datasheet - Page 20

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

HFC-U
FIFO channel operation
3.5.1
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel)
3.5.1.1 Send channels (B1, B2 and D transmit)
The send channels send data from the ISA-PC/processor bus interface to the FIFO and the HFC-U
converts the data into HDLC code and tranfers it from the FIFO into the GCI/IOM interface write
registers.
The HFC-U checks Z1 and Z2. If Z1=Z2 (FIFO empty) the HFC-U generates a HDLC-Flag (0111
1110) and sends it to the GCI/IOM interface. In this case Z2 is not incremented. If also F1=F2 only
HDLC flags are sent to the GCI/IOM interface and all counters remain unchanged. If the frame
counters are unequal F2 is incremented and the HFC-U tries to send the next frame to the output
device. After the end of a frame (Z2 reaches Z1) it automatically generates the 16 bit CRC checksum
and adds the ending flag. If there is another frame in the FIFO (F1
F2) the F2 counter is
incremented.
With every byte you send to the FIFO via the ISA-PC bus interface Z1 is incremented automatically.
If a complete frame has been send F1 must be incremented to send the next frame. If the frame
counter F1 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and
F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3).
Z1(F1) is used for the frame which is just written from the PC-bus side. Z2(F2) is used for the frame
which is just beeing transmitted to the GCI/IOM side of the HFC-U. Z1(F2) is the end of frame
pointer of the current output frame.
In the send channels F1 is only changed from the PC interface side if the software driver wants to say
„end of send frame“. Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start
address of the next frame. Z1(F2) and Z2(F2) can not be accessed.
March 1997
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