HFC-U Cologne Chip AG, HFC-U Datasheet - Page 33

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

March 1997
Name
INT_S1
Reading the INT_S1 register resets all active read interrupts. New interrupts may occur during
read. These interrupts are reported at the next read of INT_S1.
The interrupt output goes inactive during the read of INT_S1. If interrupts occur during this
read the interrupt line goes active immediately after the read is finished. So processors with
level or transition triggered interrupt inputs can be connected.
important!
(1Eh)
Bits
0
1
2
3
4
5
6
7
r/w
r
r
r
r
r
r
r
r
Function
B1-channel interrupt sta tus in transmit direction
B2-channel interrupt status in transmit direction
D-channel interrupt status in transmit direction
'1'
B1-channel interrupt status in receive direction
B2-channel interrupt status in receive direction
D-channel interrupt status in receive direction
'1'
receiver ready (RxR) of monitor channel
'1'
timer interrupt status
'1'
in HDLC mode:
in transparent mode, external RAM 32K x 8:
in transparent mode, external RAM 8K x 8:
in HDLC mode:
in transparent mode, external RAM 32K x 8:
in transparent mode, external RAM 8K x 8:
'1' a complete frame was transmitted, the frame counter
'1' bit12 in Z2 counter changed from '0' to '1'
'1' bit10 in Z2 counter changed from '0' to '1'
'1' a complete frame was transmitted, the frame counter
'1' bit12 in Z1 counter changed from '0' to '1'
'1' bit10 in Z1 counter changed from '0' to '1'
F2 was incremented
a complete frame was transmitted, the framecounter
F2 was incremented
F1 was incremented
a complete frame was received, the frame counter
F1 was incremented
2 monitor bytes have been received
timer is elapsed
HFC-U
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