HFC-U Cologne Chip AG, HFC-U Datasheet - Page 31

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

March 1997
Name
CTMT
INT_M1
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'.
(19h)
(1Ah)
Bits
2
4, 3
5
6
7
0
1
2
3
4
5
6
7
r/w
w
w
w
w
w
w
w
w
w
w
w
w
w
Function
data output to pin OUT0
'0'
select timer and watchdog
'00'
'01'
'10'
'11'
timer/watchdog reset mode
'0'
'1'
data output to pin OUT1
'0'
reset timer/WD
'1'
The bit is automatically cleared.
interrupt mask for channel B1 in transmit direction
interrupt mask for channel B2 in transmit direction
interrupt mask for channel D in transmit direction
interrupt mask for channel B1 in receive direction
interrupt mask for channel B2 in receive direction
interrupt mask for channel D in receive direction
interrupt mask for receive ready (RxR) of monitor channel
interrupt mask for timer
(reset default)
timer
25ms
50ms
400ms
800ms
reset timer/WD by CTMT bit 7 (reset default)
automatically reset timer/WD at each access to
HFC-U
(reset default)
reset timer/WD
watchdog
50ms (reset default)
100ms
800ms
1600ms
HFC-U
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