MAX17480 Maxim Integrated Products, MAX17480 Datasheet - Page 45

• Manufacturer Part Number: MAX17480
• Description: AMD 2-/3-Output Mobile Serial VID Controller
• Manufacturer: Maxim Integrated Products

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A complete command consists of a START condition
(S) followed by the MAX17480’s slave address and a
data phase, followed by a STOP condition (P). For the
slave address, bits 6:4 are always 110 and bit 3 is X
(don’t care). The WR bit should always be 1 since read
functions are not supported. Figure 14 is the SVI bus
data-transfer summary. Table 7 is a description of the
SVI send byte address and Table 8 describes serial
VID 8-bit field encoding.
Figure 14. SVI Bus Data Transfer Summary
Table 7. SVI Send Byte Address Description
BIT
6:4
3
2
1
0
Always 110b.
X—don’t care.
VDD1, if set then the following data byte
contains the VID for VDD1. Bit 2 is ignored in
combined mode (GNDS1 or GNDS2 = V
VDD1 refers to CORE1 of the AMD CPU.
VDD0, if set then the following data byte
contains the VID for VDD0 in separate mode, and
the unified VDD in combined mode. VDD0 refers
to CORE0 of the AMD CPU.
VDDNB, if set then the following data byte
contains the VID for VDDNB.
______________________________________________________________________________________
START
S
DESCRIPTION
FIXED VALUES
SLAVE ADDRESS
Command Byte
AMD 2-/3-Output Mobile Serial
DDIO
).
The minimum input operating voltage (dropout voltage)
is restricted by stability requirements, not the minimum
off-time (t
slope compensation, so the controller becomes unsta-
ble with duty cycles greater than 50% per phase:
However, the controller can briefly operate with duty
cycles over 50% during heavy load transients.
Table 8. Serial VID 8-Bit Field Encoding
BIT
6:0
7
SMPS Applications Information
SET DAC AND PSI_L
OFF(MIN)
PSI_L: Power-Save Indicator
0 means the processor is at an optimal load and
the SMPS(s) can enter power-saving mode. The
SMPS operates in pulse-skipping mode after
exiting the boot mode. Offset is disabled if
previously enabled by the OPTION pin. The
MAX17480 enters 1-phase operation if in
combined mode (GNDS1 or GNDS2 = H).
1 means the processor is in a high current-
consumption state. The SMPS operates in forced-
PWM mode after exiting the boot mode. Offset is
enabled if previously enabled by the OPTION
pin. The MAX17480 returns to 2-phase operation
if in combined mode (GNDS1 or GNDS2 = H).
SVID[6:0] as defined in Table 7.
V
IN(MIN)
). The MAX17480 does not include
VID Controller
≥ 2V
DESCRIPTION
OUT(MAX)
Minimum Input Voltage
Duty-Cycle Limits
STOP
P
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