MAX17480 Maxim Integrated Products, MAX17480 Datasheet - Page 43

• Manufacturer Part Number: MAX17480
• Description: AMD 2-/3-Output Mobile Serial VID Controller
• Manufacturer: Maxim Integrated Products

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The capacitance value required is determined primarily
by the stability requirements. However, the soar and
sag calculations are still provided here for reference.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from or added to
the output filter capacitors by a sudden load step.
Therefore, the amount of output soar and sag when the
load is applied or removed is a function of the output
voltage and inductor value. The soar and sag voltages
are calculated as:
:
where D
SMPS as listed in the Electrical Characteristics table,
t
OSC pin, and ∆t equals V
PWM mode, or L x I
skipping mode.
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V
load transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot at
the rising load edge is no longer a problem.
The input capacitor must meet the ripple-current require-
ment (I
requirements can be determined by the following equation:
:
The worst-case RMS current requirement occurs when
operating with V
equation simplifies to I
For most applications, nontantalum chemistries
(ceramic, aluminum, or OS-CON) are preferred due to
their resistance to inrush surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. The MAX17480 NB regulator is operated
as the second stage of a two-stage power-conversion
system. Tantalum input capacitors are acceptable.
Choose an input capacitor that exhibits less than 10°C
temperature rise at the RMS input current for optimal
circuit longevity.
SW3
V
SAG
3
is the NB switching period programmed by the
=
RMS
2
I
RMS
C
MAX
OUT
) imposed by the switching currents. The I
(
∆
=
3
I
is the maximum duty cycle of the NB
(
L L OAD MAX
⎛
⎜
⎝
V
V
I
IN
IN3
SOAR
LOAD
3
V
______________________________________________________________________________________
IN
×
3
(
SOAR
LX3MIN
= 2V
3
D
3
MAX
3
RMS
=
⎞
⎟
⎠
(
)
)
∆
NB Input Capacitor Selection
2
OUT3
OUT
I
−
from causing problems during
2
V
LOAD MAX
L
= 0.5 x I
/(V
V
V
OUT
3
OUT
OUT
/V
IN
. At this point, the above
3
3
3
3
IN
(
C
)
- V
(
OUT
+
V
x t
IN
∆
LOAD3
)
OUT
)
I
3
SW
2
3
L L OAD MAX
L
−
3
) when in pulse-
V
when in forced-
OUT
3
.
(
C
OUT
AMD 2-/3-Output Mobile Serial
3
)
(
)
3
t
SW
3
−
RMS
∆
t
)
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor’s power-dissipation
requirements. For NB, the load line is generated by
sensing the inductor current through the high-side
MOSFET on-resistance (R
preset to -5.5mV/A (typ). This guarantees the output
voltage to stay in the static regulation window over the
maximum load conditions per AMD specifications. See
Table 6 for full-load voltage droop according to differ-
ent ILIM3 settings.
The voltage-positioned load-line of the NB SMPS also
provides the AC ripple voltage required for stability. To
maintain stability, the output capacitive ripple must be
kept smaller than the internal AC ripple voltage. Hence,
a minimum NB output capacitance is required as calcu-
lated below:
:
where R
Electrical Characteristics table, and f
switching frequency programmed by the OSC pin.
The MAX17480 is a receive-only device. The 2-wire seri-
al bus (pins SVC and SVD) is designed to attach on a
low-voltage I
the CPU directly drives the bus at a speed of 3.4MHz.
The CPU has a push-pull output driving to the V
voltage level. External pullup resistors are not required.
When not used in the specific AMD application, the ser-
ial interface can be driven to as high as 2.5V, and can
operate at the lower speeds (100kHz, 400kHz, or
1.7MHz). At lower clock speeds, external pullup resis-
tors can be used for open-drain outputs. Connect both
SVC and SVD lines to V
resistors. Calculate the required value of the pullup
resistors using:
:
where t
the clock period. C
The MAX17480 is compatible with the standard SVI inter-
face protocol as defined in the following subsections.
Figure 12 shows the SVI bus START, STOP, and data
change conditions.
C
OUT
R
is the rise time, and should be less than 10% of
DROOP3(MIN)
SVI Applications Information
3
>
2
C-like bus. In the AMD mobile application,
2
×
NB Steady-State Voltage Positioning
f
SW
I
BUS
2
R
C Bus-Compatible Interface
NB Transient Droop and Stability
PULLUP
3
VID Controller
×
is the total capacitance on the bus.
R
DDIO
is 4mV/A as defined in the
1
DROOP MIN
ON(NH3)
≤
C
through individual pullup
BUS
3
t
R
(
), and is internally
)
⎛
⎝ ⎜
1
SW3
+
V
V
OUT
IN
is the NB
3
3
⎞
⎠ ⎟
DDIO
43