MAX17480 Maxim Integrated Products, MAX17480 Datasheet - Page 42

• Manufacturer Part Number: MAX17480
• Description: AMD 2-/3-Output Mobile Serial VID Controller
• Manufacturer: Maxim Integrated Products

www.DataSheet4U.com
AMD 2-/3-Output Mobile Serial
VID Controller
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
where N is the number of high-side MOSFETs used for
one SMPS, and Q
MOSFET’s data sheet. For example, assume two
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a single
IRF7811W has a maximum gate charge of 24nC (V
5V). Using the above equation, the required boost
capacitance would be:
:
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
:
where I
the switching frequency of the NB regulator.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. If using
a swinging inductor (where the inductance decreases
linearly with increasing current), evaluate the LIR with
properly scaled inductance values. For the selected
inductance value, the actual peak-to-peak inductor rip-
ple current (∆I
:
Ferrite cores are often the best choice, although pow-
dered iron is inexpensive and can work well at 200kHz.
The core must be large enough not to saturate at the
peak inductor current (I
42
______________________________________________________________________________________
LOAD3(MAX)
I
∆I
L
PEAK
3
INDUCTOR
=
INDUCTOR
⎛
⎜
⎜
⎝
C
3
f
BST
SW LOAD MAX
=
GATE
C
I
3
V
LOAD MAX
is the maximum current and f
BST
NB SMPS Design Procedure
I
=
IN
3
=
is the gate charge specified in the
2 24
PEAK3
200
−
) is defined by:
=
×
V
3
OUT
V
(
N Q
3
OUT
mV
(
×
200
nC
V
3
):
IN SW
)
3
(
+
GATE
mV
V
= .
)
NB Inductor Selection
3
LIR
⎛
⎜
⎝
IN
f
0 24µ
∆
3
I
INDUCTOR
⎞
⎟
⎟
⎠
−
3 3
⎛
⎜
⎝
L
V
V
2
F
OUT
OUT
V
IN
3
3 3
3
)
⎞
⎟
⎠
⎞
⎟
⎠
SW3
GS
is
=
The MAX17480 NB regulator overcurrent protection
employs a peak current-sensing algorithm that uses the
high-side MOSFET R
ment. Since the controller limits the peak inductor cur-
rent, the maximum average load current is less than the
peak current-limit threshold by an amount equal to half
the inductor ripple current. Therefore, the maximum
load capability is a function of the current-limit setting,
inductor value, switching frequency, and input-to-out-
put voltage difference. When combined with the output
undervoltage-protection circuit, the system is effectively
protected against excessive overload conditions.
The peak current-limit threshold is set by the ILIM3 pin
setting (see the Offset and Current-Limit Setting for NB
SMPS (ILIM3) section).
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements. In
CPU V
output is subject to large load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance:
:
The output capacitor’s size often depends on how
much ESR is needed to maintain an acceptable level of
output ripple voltage. The output ripple voltage of a
step-down controller equals the total inductor ripple
current multiplied by the output capacitor’s ESR. For
single-phase operation, the maximum ESR to meet the
output-ripple-voltage requirement is:
:
where f
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, capacitor selection
is usually limited by ESR and voltage rating rather than
by capacitance value (this is true of polymer types).
CORE
SW3
R
ESR
converters and other applications where the
is the switching frequency. The actual
(
≤
R
NB Peak Inductor Current Limit (ILIM3)
ESR
⎡
⎢
⎢
⎣
(
V
IN
+
3
R
ON(NH3)
V
−
PCB
IN SW
NB Output Capacitor Selection
V
3
OUT
f
)
≤
3
3 3
∆
L
)
as the current-sense ele-
I
V
LOAD MAX
OUT
V
STEP
3
(
⎤
⎥
⎥
⎦
V
RI
)
P P PLE3