ATA8742 ATMEL Corporation, ATA8742 Datasheet - Page 75

• Manufacturer Part Number: ATA8742
• Manufacturer: ATMEL Corporation

9151A–INDCO–07/09
Figure 19-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd, max and tpd,min, a single signal transition on the pin will be
delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
positive edge of the clock. In this case, the delay tpd through the synchronizer is one system
clock period.
Figure 19-4. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
Figure 19-4 on page
PINxn
PINxn
r17
r16
r17
out PORTx, r16
75. The out instruction sets the “SYNC LATCH” signal at the
XXX
t
pd, max
0x00
0x00
XXX
nop
t
pd
t
0xFF
pd, min
in r17, PINx
in r17, PINx
ATA8742
0xFF
0xFF
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