ATA8742 ATMEL Corporation, ATA8742 Datasheet - Page 60

• Manufacturer Part Number: ATA8742
• Manufacturer: ATMEL Corporation

16.1
16.1.1
16.2
60
Watchdog Timer
Internal Voltage Reference
ATA8742
Voltage Reference Enable Signals and Start-up Time
ATtiny24/44/84 features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
16-4 on page
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny24/44/84 resets and executes from the Reset Vec-
tor. For timing details on the Watchdog Reset, refer to
The watchdog timer can also be configured to generate an interrupt instead of a reset. This can
be very helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 16-2. See
Sequences for Changing the Configuration of the Watchdog Timer” on page 61
Table 16-2.
WDTON
Unprogrammed
Programmed
ACBG bit in ACSR).
64. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
WDT Configuration as a Function of the Fuse Settings of WDTON
Safety
Level
“System and Reset Characterizations” on page
1
2
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
Table 16-4 on page
198. To save power, the
How to Change
Time-out
No limitations
Timed sequence
64.
for details.
9151A–INDCO–07/09
“Timed
Table