ATA8742 ATMEL Corporation, ATA8742 Datasheet - Page 100

• Manufacturer Part Number: ATA8742
• Manufacturer: ATMEL Corporation

20.9
20.9.1
100
Register Description
ATA8742
TCCR0A – Timer/Counter Control Register A
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting.
WGM02:0 bits are set to a normal or CTC mode (non-PWM).
Table 20-2.
Table 20-3 on page 100
to fast PWM mode.
Table 20-3.
Note:
Bit
0x30 (0x50)
Read/Write
Initial Value
COM01
COM01
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at BOTTOM. See
page 95
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
COM0A1
R/W
7
0
COM00
COM00
for more details.
1
0
1
0
1
0
1
0
Table 20-2 on page 100
COM0A0
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set
R/W
6
0
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on Compare Match
Clear OC0A on Compare Match
Set OC0A on Compare Match
Description
Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
Clear OC0A on Compare Match, set OC0A at BOTTOM
(non-inverting mode)
Set OC0A on Compare Match, clear OC0A at BOTTOM
(inverting mode)
COM0B1
R/W
5
0
COM0B0
R/W
4
0
shows the COM0A1:0 bit functionality when the
R
3
0
–
(1)
R
2
–
0
WGM01
R/W
1
0
“Fast PWM Mode” on
WGM00
R/W
9151A–INDCO–07/09
0
0
TCCR0A