ATA6602 ATMEL Corporation, ATA6602 Datasheet - Page 156
ATA6602
Manufacturer Part Number
ATA6602
Description
LIN and Microcontroller System-In-Package: LIN Transceiver, integrated 5V/50 mA voltage regulator, window watchdog and automotive AVR ATmega88 (8 kBytes Flash); green QFN48 package.
Manufacturer
ATMEL Corporation
Datasheet
1.ATA6602.pdf
(362 pages)
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4.14.10.4
4.14.10.5
4.14.10.6
156
ATA6602/ATA6603
Timer/Counter1 – TCNT1H and TCNT1L
Output Compare Register 1 A – OCR1AH and OCR1AL
Output Compare Register 1 B – OCR1BH and OCR1BL
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers see
Registers” on page
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-
pare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers (see
Initial Value
Initial Value
Initial Value
Read/Write
Read/Write
Read/Write
Bit
Bit
Bit
R/W
R/W
R/W
7
0
7
0
7
0
132.
“Accessing 16-bit Registers” on page
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
OCR1A[15:8]
OCR1B[15:8]
TCNT1[15:8]
4
0
4
OCR1A[7:0]
0
4
OCR1B[7:0]
0
TCNT1[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
132).
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
“Accessing 16-bit
R/W
R/W
R/W
0
0
0
0
0
0
4921C–AUTO–01/07
OCR1AH
OCR1BH
OCR1AL
OCR1BL
TCNT1H
TCNT1L
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