ATA25 White Electronic Designs Corporation, ATA25 Datasheet - Page 4

• Manufacturer Part Number: ATA25
• Description: Density = 32MB-1GB ;; Memory Device = Hitachi Flash ;; Organization = X16/x8 ;; Speed (ns) = 250 ;; Volt = 3/5
• Manufacturer: White Electronic Designs Corporation

7PxxxATA25xxC25
Card Pin Explanation
Address bus (A0 to A10: input): Address bus is A0 to A10. A0 is invalid in word mode. A10 is MSB
and A0 is LSB. In True IDE Mode only HA [2 : 0] are used for selecting the one of eight registers in the
Task File, the remaining address lines should be grounded.
Data bus (D0 to D15: input/output): Data bus is D0 to D15. D0 is the LSB of the Even Byte of the
Word. D8 is the LSB of the Odd Byte of the Word.
Card enable (-CE1, -CE2: input): -CE1 and -CE2 are low active card select signals. Even addresses are
controlled by -CE1 and odd addresses are by -CE2. In True IDE Mode -CE2 is used for select the
Alternate Status Register and the Device Control Register while -CE1 is the chip select for the other task
file registers.
Output enable, ATA select (-OE, -ASTEL: input): -OE is used for the control of data read in Attribute
area or Common memory area. To enable True IDE Mode this input should be grounded by the host.
Write enable (-WE: input): -WE is used for the control of data write in Attribute memory area or
Common memory area. In True IDE Mode this input signal is not used and should be connected to VCC.
I/O read (-IORD: input): -IORD is used for control of read data in the Task File area. This card does
not respond to -IORD until I/O card interface setting up.
I/O write (-IOWR: input): -IOWR is used for control of data write in the Task File area. This card does
not respond to -IOWR until I/O card interface setting up.
Ready/Busy, Interrupt request (RDY/-BSY, -IREQ, INTRQ: output): In the I/O card mode, this signal
is -IREQ pin. The signal of low level indicates that the card is requesting software service to the host, and
high level indicates that the card is not requesting. In memory card mode, the signal is RDY/-BSY pin.
RDY/-BSY pin turns low level during the card internal initialization operation at V
applied or reset
CC
applied, so the next access to the card should be after the signal turns high level. In True IDE Mode signal
is the active high Interrupt Request to the host.
Card detection (-CD1, -CD2: output): -CD1 and -CD2 are the card detection signals. -CD1 and -CD2
are connected to ground in this card, so the host can detect if the card is inserted or not.
Write protect, 16 bit I/O port (WP, -IOIS16: output): In memory card mode, WP is held low because
this card does not have a write protect switch. In the I/O card mode, -IOIS16 is asserted when Task File
registers are accessed in 16-bit mode. In True IDE Mode this output signal is asserted low when this
device is expecting a word data transfer cycle.
Attribute memory area selection (-REG: input): -REG should be high level during common memory
area accessing, and low level during Attribute area accessing. The attribute memory area is located only in
an even address, so D0 to D7 are valid and D8 to D15 are invalid in the word access mode. Odd addresses
are invalid in the byte access mode. In True IDE Mode this input signal is not used and should be
connected to VCC.
June 2000 Rev. 1 – ECO #12936
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