78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 5

• Manufacturer Part Number: 78Q2120
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

10/100BASE-TX
Ethernet Transceiver
The receive clock, RX_CLK, provides the timing
reference to transfer RX_DV, RXD[3:0], and RX_ER
signals from the 78Q2120-64CGT to the MAC.
RX_DV transitions synchronously with respect to
RX_CLK and is asserted when the 78Q2120-64CGT
is presenting valid data on RXD[3:0].
asserted when a code group violation has been
detected in the current receive packet and is also
synchronous to RX_CLK.
Station Management Interface
The station management interface consists of
circuitry which implements the serial protocol as
described in Clause 22.2.4.4 of IEEE-802.3. A 16-bit
shift register receives serial data applied to the
MDIO pin at the rising edge of the MDC clock signal.
Once
management control logic looks for the start-of-
frame sequence and a read or write op-code,
followed by the PHYAD and REGAD fields. For a
read operation, the MDIO port becomes enabled as
an output and the register data is loaded into a shift
register for transmission. The 78Q2120-64CGT can
work with a one bit preamble rather than the 32 bits
proscribed by IEEE-802.3.
programming of the registers. If a register does not
exist at an address indicated by the REGAD field or
if the PHYAD field does not match the 78Q2120-
64CGT PHYAD indicated by the PHYAD pins, a
read of the MDIO port will return all ones. For a write
operation, the data is shifted in and loaded into the
appropriate register after the sixteenth data bit has
been received. Writes to registers not supported by
the 78Q2120-64CGT are ignored.
the
preamble
is
received,
This allows for faster
the
RX_ER is
station
5
When the PHYAD field is all zeros, the Station
Management Entity (STA) is requesting a broadcast
data transaction.
Management
broadcast request.
respond to the broadcast data transaction.
ADDITIONAL FEATURES
LED Indicators
There are seven LED pins that can be used to
indicate various states of operation of the 78Q2120-
64CGT. There is an LED pin that indicates the link
is up ( LEDL ), others that indicates the 78Q2120-
64CGT is either transmitting ( LEDTX ) or receiving
( LEDRX ), one that signals a collision event
( LEDCOL ), two more that reflect the data rate
( LEDBTX and LEDBT ), and one that reflects full
duplex mode of operation ( LEDFDX ).
Interrupt Pin
The 78Q2120-64CGT has an Interrupt pin (INTR)
that is asserted whenever any of the eight interrupt
bits of MR17.7:0 are set. These interrupt bits can be
disabled via MR17.15:8 Interrupt Enable bits. The
active level of the INTR pin is controlled by the
Interrupt Level bit, MR16.14. When the INTR pin is
not asserted, the pin is held in a high impedance
state.
Interface
All PHYs sharing the same
All
must
78Q2120-64CGT
respond
to
this
will