78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 2

• Manufacturer Part Number: 78Q2120
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

FUNCTIONAL DESCRIPTION
GENERAL
Power Management
The 78Q2120-64CGT has three power saving
modes:
Chip power-down is activated by setting the PWRDN
bit in the MII register (MR0.11) or pulling high the
PWRDN pin.
mode, all on-chip circuitry is shut off, and the device
consumes minimum power. While in power-down
state,
management transactions.
Receive power management (RXCC mode) is
activated by setting the RXCC bit in the MII register
(MR16.0). In this mode of operation, the adaptive
equalizer, the clock recovery phase lock loop (PLL),
and all other receive circuitry will be powered down
when no valid signal is present at the UTP receive
line interface. As soon as a valid signal is detected,
all circuits will automatically be powered up to
resume normal operation.
operation, RX_CLK will be inactive when there is no
data being received. Note that the RXCC mode is
not supported during 10BASE-T operation.
Transmit high impedance mode is activated by
setting the TXHIM bit in the MII register (MR16.12).
In this mode of operation, the transmit UTP drivers
are in a high impedance state and TXCLK is tri-
stated. A weak internal pull-up is enabled on TXCLK.
The receive circuitry remains fully operational. The
default state of MR16.12 is a logic low for disabling
the transmit high impedance mode. Only a reset
condition will automatically clear MR16.12. The
transmitter is fully functional when MR16.12 is
cleared.
Analog Biasing
The 78Q2120-64CGT uses the reference clock and
an external resistor to generate accurate bias
voltages for the chip.
Clock Selection
The 78Q2120-64CGT will default to use the on-chip
crystal oscillator. In this mode a 25MHz crystal is
connected between the XTLP and XTLN pins. The
•
•
•
the
Chip Power-Down
Receive Power Management
Transmit High Impedance Mode
78Q2120-64CGT
When the chip is in power-down
During this mode of
still
responds
to
2
CKIN pin should be tied low. Alternatively, an
externally generated 25MHz clock can be connected
to the CKIN pin. The chip senses activity on the CKIN
pin, and will automatically configure itself to use the
external clock. In this mode of operation, a crystal is
not required and the XTLP and XTLN pins should be
connected together.
Transmit Clock Generation
The
synthesizer to generate the transmit clock. In
100BASE-TX operation, the synthesizer multiplies the
reference clock by 5 to obtain the internal 125MHz
serial transmit clock. In 10BASE-T mode, it generates
an internal 20MHz transmit clock by multiplying the
reference 25MHz clock by 4/5. The synthesizer
references either the local 25 MHz crystal oscillator,
or the externally applied clock, depending on the
selected mode of operation.
Receive Signal Qualification
The integrated signal qualifier has separate squelch
and un-squelch thresholds, and includes a built-in timer
to ensure fast and accurate signal detection and
receive noise rejection. Upon detection of two or more
valid 10BASE-T or 100BASE-TX pulses on the line
receive port, the pass indication, indicating the
presence of valid receive signals or data will be
asserted. When pass is asserted, the signal detect
threshold is lowered by about 60%, and all adaptive
circuits are released from their quiescent operating
conditions, allowing them to lock onto the incoming
data. In 100BASE-TX operation, pass will be de-
asserted when no signal is presented for a period of
about 1.2us. In 10BASE-T operation, pass will be de-
asserted whenever no Manchester data is received. In
either case, the signal detect threshold will return to the
squelched level whenever the pass indication is de-
asserted. The pass signal is used internally to control
the operation of the receive clock recovery.
Receive Clock Recovery
In 100BASE-TX mode, the 125MHz receive clock is
extracted using a narrow-band PLL. When no receive
signal is present, the PLL is directed to lock onto the
transmit 125 MHz clock. When pass is asserted, the
PLL will use the received NRZI signal as the clock
reference. The recovered clock is used to re-time the
data signal and for conversion of the data to NRZ
format.
In 10BASE-T mode, the 10MHz clock is recovered
using a PLL. For fast acquisition, the receive PLL is
locked onto the transmit reference clock during idle
transmitter
Ethernet Transceiver
uses
10/100BASE-TX
an
on-chip
frequency