78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 16

• Manufacturer Part Number: 78Q2120
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

MR16 - VENDOR SPECIFIC REGISTER (continued)
16.3:2
16.1
16.0
16.7
16.6
16.5
16.4
BIT
SYMBOL
RVSPOL
PCSBP
RSVD
RSVD
RSVD
RXCC
APOL
R, (W), 0
R, W, 0
R,W,00
R,W,0
R,W,0
TYPE
R, 0
R, 1
DESCRIPTION
RESERVED
RESERVED
AUTO POLARITY: During auto-negotiation and 10BASE-T mode,
the 78Q2120-64CGT is able to automatically invert the received
signal - both the Manchester data and link pulses - if necessary.
Setting this bit disables this feature.
REVERSE POLARITY: The reverse polarity is detected either
through 8 inverted 10BASE-T link pulses (NLP) or through one burst
of inverted fast link pulses (FLP). When the reverse polarity is
detected, the 78Q2120-64CGT will invert the receive data path and
set this bit to logic one if the feature is not disabled. If APOL is a
logic 1, then this bit is write-able. Setting this bit forces the polarity
to be reversed.
RESERVED. Must be zero.
PCS BYPASS: When set, the 100BASE-TX PCS is bypassed, as
are the scrambler and descrambler functions. Scrambled 5-bit code
groups for transmission are applied to the TX_ER, TXD[3:0] pins
and received on the RX_ER, RXD[3:0] pins. The RX_DV and
TX_EN signals are not valid in this mode. PCSBP mode is only valid
when 100BASE-TX is enabled.
RECEIVE CLOCK CONTROL: When set, the RX_CLK signal will
be held in logic low (only in 100BASE-TX mode) when there is no
data being received (to save power). The RX_CLK signal will restart
1 clock cycle before the assertion of RX_DV and be shut off 64 clock
cycles after RX_DV goes low. RXCC is disabled when loopback
mode is enabled (MR0.14 is high). This bit should be kept at logic
zero when the chip is in PCS Bypass mode.
16
Ethernet Transceiver
10/100BASE-TX