XR17C158 Exar Corporation, XR17C158 Datasheet - Page 33

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

XR17C158
REV. 1.0.0
The UART provides multiple levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with
six interrupt status bits. Performing a read cycle on
the ISR will give the user the current highest pending
interrupt level to be serviced, others queue up for
next service. No other interrupts are acknowledged
until the pending interrupt is serviced. The Interrupt
Source Table, Table 12, shows the data values (bit 0-
5) for the six prioritized interrupt levels and the inter-
rupt sources associated with each of these interrupt
levels.
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by the a 4-char plus 12 bits
• TXRDY is by LSR bit-5 (or bit-6 in auto RS485 con-
• MSR is by any of the MSR bits, 0, 1, 2 and 3.
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR con-
tents may be used as a pointer to the appropriate in-
terrupt service routine.
Logic 1 = No interrupt pending. (default condition)
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a log-
ic 1. ISR bit-4 indicates that the receiver detected a
data match of the Xon or Xoff character(s).
4.11 I
P
4.11.1 Interrupt Generation:
delay timer if data doesn’t reach FIFO trigger level.
trol).
L
RIORITY
EVEL
X
1
2
3
4
5
6
7
NTERRUPT
Table
B
IT
0
0
0
0
0
0
1
0
12).
PCI BUS OCTAL UART
-5
S
TATUS
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
R
EGISTER
B
T
EGISTER
IT
0
0
1
0
0
0
0
0
ABLE
-3
(ISR)
12: I
B
S
IT
TATUS
1
1
1
0
0
0
0
0
-2
NTERRUPT
B
B
ITS
IT
1
0
0
1
0
0
0
0
-1
S
OURCE AND
33
B
• Receive Xon/Xoff/Special character is by detection
• CTS#/DSR# is by a change of state on the input pin
• RTS#/DTR# is when its receiver changes the state
• LSR interrupt is cleared by a read to the LSR regis-
• RXRDY and RXRDY Time-out are cleared by read-
• TXRDY interrupt is cleared by a read to the ISR
• MSR interrupt is cleared by a read to the MSR reg-
• Xon, Xoff or Special character interrupt is cleared
• RTS#/DTR# and CTS#/DSR# status change inter-
N
a logic 1 until a Xon character is received. ISR bit-5 indi-
cates that CTS#/DSR# or RTS#/DTR# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are
disabled. They are set to a logic 1 when the FIFOs
are enabled.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
IT
0
0
0
0
0
0
0
1
4.11.2 Interrupt Clearing:
OTE
of a Xon, Xoff or Special character.
with auto flow control enabled, EFR bit-7, and
depending on selection on MCR bit-2.
of the output pin during auto RTS/DTR flow control
enabled by EFR bit-6 and selection of MCR bit-2.
ter.
ing data until FIFO falls below the trigger level.
register.
ister.
by a read to ISR.
rupts are cleared by a read to the MSR register.
-0
: Note that once set to a logic 1, the ISR bit-4 will stay
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xon/Xoff or Special character)
CTS#/DSR#, RTS#/DTR# change of state
None (default)
P
RIORITY
S
L
OURCE OF THE INTERRUPT
EVEL
PRELIMINARY
+